From patchwork Mon Jan 18 12:36:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "G.N, Vijayakumar" X-Patchwork-Id: 73653 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o0ICauPt006229 for ; Mon, 18 Jan 2010 12:36:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753172Ab0ARMgz (ORCPT ); Mon, 18 Jan 2010 07:36:55 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752385Ab0ARMgz (ORCPT ); Mon, 18 Jan 2010 07:36:55 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:45765 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751490Ab0ARMgy convert rfc822-to-8bit (ORCPT ); Mon, 18 Jan 2010 07:36:54 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o0ICaoem014933 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 18 Jan 2010 06:36:52 -0600 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o0ICaoWJ006823; Mon, 18 Jan 2010 18:06:50 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Mon, 18 Jan 2010 18:06:50 +0530 From: "G.N, Vijayakumar" To: "linux-omap@vger.kernel.org" , "khilman@deeprootsystems.com" CC: "Sripathy, Vishwanath" , "Turquette, Mike" Date: Mon, 18 Jan 2010 18:06:31 +0530 Subject: [PATCHV2 2/2] OMAP3630: Clock: Fixing HSDivider Limitation Thread-Topic: [PATCHV2 2/2] OMAP3630: Clock: Fixing HSDivider Limitation Thread-Index: AcqYOm1PM1P90NSxTtyo0cA1SYPpgAAAC9oA Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 0d30e53..e5213f8 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -146,6 +146,42 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = { .find_companion = omap2_clk_dflt_find_companion, }; +/** omap3_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering + * from HSDivider problem. + * @clk: DPLL output struct clk + * + * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, dpll4_m5_ck + * & dpll4_m6_ck dividers get lost after their respective PWRDN bits are set. + * Any write to the corresponding CM_CLKSEL register will refresh the + * dividers. Only x2 clocks are affected, so it is safe to trust the parent + * clock information to refresh the CM_CLKSEL registers. + */ +int omap3_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) +{ + u32 v; + int ret; + + /* enable the clock */ + ret = omap2_dflt_clk_enable(clk); + + /* Restore the dividers */ + if (!ret) { + v = __raw_readl(clk->parent->clksel_reg); + v += (1 << clk->parent->clksel_shift); + __raw_writel(v, clk->parent->clksel_reg); + v -= (1 << clk->parent->clksel_shift); + __raw_writel(v, clk->parent->clksel_reg); + } + return ret; +} + +const struct clkops clkops_omap3_pwrdn_with_hsdiv_wait_restore = { + .enable = omap3_pwrdn_clk_enable_with_hsdiv_restore, + .disable = omap2_dflt_clk_disable, + .find_companion = omap2_clk_dflt_find_companion, + .find_idlest = omap2_clk_dflt_find_idlest, +}; + const struct clkops clkops_noncore_dpll_ops = { .enable = omap3_noncore_dpll_enable, .disable = omap3_noncore_dpll_disable, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 9a2c07e..6f7d271 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -20,5 +20,6 @@ extern const struct clkops clkops_omap3430es2_ssi_wait; extern const struct clkops clkops_omap3430es2_hsotgusb_wait; extern const struct clkops clkops_omap3430es2_dss_usbhost_wait; extern const struct clkops clkops_noncore_dpll_ops; +extern const struct clkops clkops_omap3_pwrdn_with_hsdiv_wait_restore; #endif diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 955d4ef..39a1b3c 100755 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -3447,6 +3447,21 @@ int __init omap2_clk_init(void) dpll4_m4_ck = dpll4_m4_ck_3630; dpll4_m5_ck = dpll4_m5_ck_3630; dpll4_m6_ck = dpll4_m6_ck_3630; + + /* For 3630: override clkops_omap2_dflt_wait for the + * clocks affected from HSDivider PWRDN reset limitation */ + dpll3_m3x2_ck.ops = + &clkops_omap3_pwrdn_with_hsdiv_wait_restore; + dpll4_m2x2_ck.ops = + &clkops_omap3_pwrdn_with_hsdiv_wait_restore; + dpll4_m3x2_ck.ops = + &clkops_omap3_pwrdn_with_hsdiv_wait_restore; + dpll4_m4x2_ck.ops = + &clkops_omap3_pwrdn_with_hsdiv_wait_restore; + dpll4_m5x2_ck.ops = + &clkops_omap3_pwrdn_with_hsdiv_wait_restore; + dpll4_m6x2_ck.ops = + &clkops_omap3_pwrdn_with_hsdiv_wait_restore; } else { dpll4_dd = dpll4_dd_34xx; dpll4_m2_ck = dpll4_m2_ck_34xx;