From patchwork Thu Dec 13 14:32:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guennadi Liakhovetski X-Patchwork-Id: 1874241 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 9E6D93FC64 for ; Thu, 13 Dec 2012 14:33:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932916Ab2LMOdU (ORCPT ); Thu, 13 Dec 2012 09:33:20 -0500 Received: from moutng.kundenserver.de ([212.227.126.187]:61103 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756342Ab2LMOdQ (ORCPT ); Thu, 13 Dec 2012 09:33:16 -0500 Received: from axis700.grange (dslb-146-060-254-132.pools.arcor-ip.net [146.60.254.132]) by mrelayeu.kundenserver.de (node=mrbap3) with ESMTP (Nemesis) id 0LfjPW-1TLMUG2sOY-00okIK; Thu, 13 Dec 2012 15:32:47 +0100 Received: by axis700.grange (Postfix, from userid 1000) id 3DC9A40B99; Thu, 13 Dec 2012 15:32:46 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by axis700.grange (Postfix) with ESMTP id 3191840B98; Thu, 13 Dec 2012 15:32:46 +0100 (CET) Date: Thu, 13 Dec 2012 15:32:46 +0100 (CET) From: Guennadi Liakhovetski X-X-Sender: lyakh@axis700.grange To: Will Deacon cc: Nicolas Pitre , Dave Martin , Lorenzo Pieralisi , Russell King , "linux-sh@vger.kernel.org" , Catalin Marinas , Daniel Lezcano , Stephen Boyd , Amit Kucheria , Simon Horman , Santosh Shilimkar , Colin Cross , "linux-omap@vger.kernel.org" , Wenzeng Chen , "linux-arm-kernel@lists.infradead.org" Subject: Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations In-Reply-To: <20121213105109.GB26540@mudshark.cambridge.arm.com> Message-ID: References: <20120919134658.GA2111@linaro.org> <20120920102514.GD4588@e102568-lin.cambridge.arm.com> <20120920110439.GB2117@linaro.org> <20121211163313.GG16759@mudshark.cambridge.arm.com> <20121211163843.GH16759@mudshark.cambridge.arm.com> <50C7C16B.7050106@codeaurora.org> <20121212103338.GB23022@e102568-lin.cambridge.arm.com> <20121212133650.GJ6195@mudshark.cambridge.arm.com> <20121213105109.GB26540@mudshark.cambridge.arm.com> MIME-Version: 1.0 X-Provags-ID: V02:K0:IYy8yljryMf81mX4LbQFOyxNGCGOVArqto6iUJKaxoh I19fARIfTIpRlXmgZgU8o6xPeFztkXDmEAzpHL8qrtV2YQRRpH y0HjxHx/fI/i3RCtTkRY1nbGlfCLF/y3g5mjQWgKsPBZXf1ne/ Q6EI7WuOGxHQGMN2hmcXPECVGGHDRZy4MAn59n0R+SSZKv50x5 77H2qhlRM09yOnpi5YOcCb2uR6EF6pxwI4C9EbDYn4IU3pwUpf 6j7gIGMegSL762QO+s4ntRI7n6k45geY7lkjmxokJyi2IvPd9U hKjoSMlw10gKVoOD5MGAQg6975gxgNBD2cQfi7QS6pfeJbcaqT pfmrJ5OxX00Vr3DHB6lB4eZPqzm4GaC5erCbKfTjt/LmXyn2QK 3VAA9yw9Vdd6A== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On Thu, 13 Dec 2012, Will Deacon wrote: > On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote: > > On Wed, 12 Dec 2012, Will Deacon wrote: > > > Back to the case in hand.... Lorenzo just pointed out to me that the > > > finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so > > > the louis stuff should be irrelevant. The problem may actually be that the > > > finisher disables the L2 cache prior to cleaning/invalidating it, which is > > > the opposite order to that described by the A8 TRM. > > > > > > Guennadi -- can you try moving the kernel_flush call before the L2 disable > > > in sh7372_do_idle_sysc please? > > > > Yes, this works too. > > That's good to know. Please can you send a patch for that? The sequence > currently being used by the finisher *is* buggy, and should be fixed > independently of the louis stuff. Well, the fix is yours, so, it should be "From: you." I can certainly send it just copying your description above, but I'd also need your Sob. Something like the below (feel free to improve the subject line and the description): From: Will Deacon Subject: [PATCH] ARM: sh7372: fix cache clean / invalidate order According to the Cortex A8 TRM the L2 cache should be first cleaned and then disabled. Fix the swapped order on sh7372. Signed-off-by: Signed-off-by: Guennadi Liakhovetski (or even just) Tested-by: Guennadi Liakhovetski Reviewed-by: Santosh Shilimkar --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S index 1d56467..df15d8a 100644 --- a/arch/arm/mach-shmobile/sleep-sh7372.S +++ b/arch/arm/mach-shmobile/sleep-sh7372.S @@ -59,16 +59,16 @@ sh7372_do_idle_sysc: mcr p15, 0, r0, c1, c0, 0 isb - /* disable L2 cache in the aux control register */ - mrc p15, 0, r10, c1, c0, 1 - bic r10, r10, #2 - mcr p15, 0, r10, c1, c0, 1 - /* * Invalidate data cache again. */ ldr r1, kernel_flush blx r1 + + /* disable L2 cache in the aux control register */ + mrc p15, 0, r10, c1, c0, 1 + bic r10, r10, #2 + mcr p15, 0, r10, c1, c0, 1 /* * The kernel doesn't interwork: v7_flush_dcache_all in particluar will * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.