From patchwork Wed Sep 19 13:23:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Afzal Mohammed X-Patchwork-Id: 1477461 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 8819E3FE79 for ; Wed, 19 Sep 2012 13:23:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755532Ab2ISNX3 (ORCPT ); Wed, 19 Sep 2012 09:23:29 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:37230 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754310Ab2ISNX3 (ORCPT ); Wed, 19 Sep 2012 09:23:29 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q8JDNOpn004254; Wed, 19 Sep 2012 08:23:25 -0500 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8JDNOcl028670; Wed, 19 Sep 2012 18:53:24 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Wed, 19 Sep 2012 18:53:23 +0530 Received: from psplinux051.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8JDNNs3013665; Wed, 19 Sep 2012 18:53:23 +0530 From: Afzal Mohammed To: , , , , CC: Afzal Mohammed Subject: [PATCH v7 06/11] ARM: OMAP2+: gpmc: find features by ip rev check Date: Wed, 19 Sep 2012 18:53:23 +0530 Message-ID: X-Mailer: git-send-email 1.7.12 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Newer IP's have wr_access and wr_data_mux_bus fields. Use IP revision values to determine availability of these fields and hence decide on whether to configure them. Signed-off-by: Afzal Mohammed Reviewed-by: Jon Hunter --- arch/arm/mach-omap2/gpmc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index a481816..d0916e9 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -90,6 +90,11 @@ #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 +#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) + +#define GPMC_HAS_WR_ACCESS 0x1 +#define GPMC_HAS_WR_DATA_MUX_BUS 0x2 + /* XXX: Only NAND irq has been considered,currently these are the only ones used */ #define GPMC_NR_IRQ 2 @@ -136,6 +141,7 @@ static DEFINE_SPINLOCK(gpmc_mem_lock); static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ +static unsigned gpmc_capability; static void __iomem *gpmc_base; static struct clk *gpmc_l3_clk; @@ -364,10 +370,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring); GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation); - if (cpu_is_omap34xx()) { + if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); + if (gpmc_capability & GPMC_HAS_WR_ACCESS) GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); - } /* caller is expected to have initialized CONFIG1 to cover * at least sync vs async @@ -930,6 +936,8 @@ static int __init gpmc_init(void) clk_enable(gpmc_l3_clk); l = gpmc_read_reg(GPMC_REVISION); + if (GPMC_REVISION_MAJOR(l) > 0x4) + gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); /* Set smart idle mode and automatic L3 clock gating */ l = gpmc_read_reg(GPMC_SYSCONFIG);