From patchwork Wed Dec 22 16:56:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 428191 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBMGuHjW007001 for ; Wed, 22 Dec 2010 16:56:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752546Ab0LVQ4Q (ORCPT ); Wed, 22 Dec 2010 11:56:16 -0500 Received: from utopia.booyaka.com ([72.9.107.138]:55399 "EHLO utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751292Ab0LVQ4Q (ORCPT ); Wed, 22 Dec 2010 11:56:16 -0500 Received: (qmail 21892 invoked by uid 1019); 22 Dec 2010 16:56:15 -0000 Date: Wed, 22 Dec 2010 09:56:15 -0700 (MST) From: Paul Walmsley To: Vishwanath Sripathy , rnayak@ti.com cc: linux-omap@vger.kernel.org, tony@atomide.com, khilman@deeprootsystems.com Subject: RE: [PATCHv3] OMAP3: SDRC : Add comments on Errata i520 for Global SW reset In-Reply-To: Message-ID: References: <1286287534-9160-1-git-send-email-vishwanath.bs@ti.com> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 22 Dec 2010 16:56:17 +0000 (UTC) diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index c22e726..679bcd2 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -74,6 +74,34 @@ void omap_prcm_arch_reset(char mode, const char *cmd) WARN_ON(1); } + /* + * As per Errata i520, in some cases, user will not be able to + * access DDR memory after warm-reset. + * This situation occurs while the warm-reset happens during a read + * access to DDR memory. In that particular condition, DDR memory + * does not respond to a corrupted read command due to the warm + * reset occurrence but SDRC is waiting for read completion. + * SDRC is not sensitive to the warm reset, but the interconnect is + * reset on the fly, thus causing a misalignment between SDRC logic, + * interconnect logic and DDR memory state. + * WORKAROUND: + * Steps to perform before a Warm reset is trigged: + * 1. enable self-refresh on idle request + * 2. put SDRC in idle + * 3. wait until SDRC goes to idle + * 4. generate SW reset (Global SW reset) + * + * Steps to be performed after warm reset occurs (in bootloader): + * if HW warm reset is the source, apply below steps before any + * accesses to SDRAM: + * 1. Reset SMS and SDRC and wait till reset is complete + * 2. Re-initialize SMS, SDRC and memory + * + * NOTE: Above work around is required only if arch reset is implemented + * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need + * the WA since it resets SDRC as well as part of cold reset. + */ + /* XXX should be moved to some OMAP2/3 specific code */ omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL);