From patchwork Sun Feb 10 19:19:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 2122811 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 168F93FCA4 for ; Sun, 10 Feb 2013 19:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756583Ab3BJTTL (ORCPT ); Sun, 10 Feb 2013 14:19:11 -0500 Received: from utopia.booyaka.com ([74.50.51.50]:58041 "EHLO utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756136Ab3BJTTK (ORCPT ); Sun, 10 Feb 2013 14:19:10 -0500 Received: (qmail 17666 invoked by uid 1019); 10 Feb 2013 19:19:09 -0000 Date: Sun, 10 Feb 2013 19:19:09 +0000 (UTC) From: Paul Walmsley To: Sebastien Guiriec cc: =?ISO-8859-15?Q?Beno=EEt_Cousson?= , Tony Lindgren , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peter Ujfalusi , Liam Girdwood , Tero Kristo , Jon Hunter Subject: Re: [PATCH v2 5/5] OMAP4: hwmod data: Update AESS data with memory bank area In-Reply-To: <1357743792-13917-6-git-send-email-s-guiriec@ti.com> Message-ID: References: <1357743792-13917-1-git-send-email-s-guiriec@ti.com> <1357743792-13917-6-git-send-email-s-guiriec@ti.com> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hi On Wed, 9 Jan 2013, Sebastien Guiriec wrote: > Add AESS memory bank data in hwmod in order to provide memory > address information to the driver. > > Signed-off-by: sebastien Guiriec Due to the cleanup of the CLKCTRL leaf clocks, this one has been updated to change the AESS main clock to be aess_fclk, and it's also been moved to precede the patch that enables the AESS hwmod. - Paul From: Sebastien Guiriec Date: Sun, 10 Feb 2013 11:22:24 -0700 Subject: [PATCH] ARM: OMAP4: hwmod data: Update AESS data with memory bank area Add AESS memory bank data in hwmod in order to provide memory address information to the driver. This version also changes the AESS main clock to use a non-CLKCTRL-based functional clock. These are being removed from the clock data, since they should be handled by the IP block integration code. Without this change, the kernel crashes during boot. Thanks to Tony Lindgren for reporting this during a test merge. Signed-off-by: Sebastien Guiriec [paul@pwsan.com: updated to change the AESS main_clk] Cc: Tony Lindgren Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 44 +++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index c9c251e..a30c113 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -349,7 +349,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = { .clkdm_name = "abe_clkdm", .mpu_irqs = omap44xx_aess_irqs, .sdma_reqs = omap44xx_aess_sdma_reqs, - .main_clk = "aess_fck", + .main_clk = "aess_fclk", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, @@ -4250,6 +4250,27 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { { + .name = "dmem", + .pa_start = 0x40180000, + .pa_end = 0x4018ffff + }, + { + .name = "cmem", + .pa_start = 0x401a0000, + .pa_end = 0x401a1fff + }, + { + .name = "smem", + .pa_start = 0x401c0000, + .pa_end = 0x401c5fff + }, + { + .name = "pmem", + .pa_start = 0x401e0000, + .pa_end = 0x401e1fff + }, + { + .name = "mpu", .pa_start = 0x401f1000, .pa_end = 0x401f13ff, .flags = ADDR_TYPE_RT @@ -4268,6 +4289,27 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { { + .name = "dmem_dma", + .pa_start = 0x49080000, + .pa_end = 0x4908ffff + }, + { + .name = "cmem_dma", + .pa_start = 0x490a0000, + .pa_end = 0x490a1fff + }, + { + .name = "smem_dma", + .pa_start = 0x490c0000, + .pa_end = 0x490c5fff + }, + { + .name = "pmem_dma", + .pa_start = 0x490e0000, + .pa_end = 0x490e1fff + }, + { + .name = "dma", .pa_start = 0x490f1000, .pa_end = 0x490f13ff, .flags = ADDR_TYPE_RT