b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -72,10 +72,26 @@ static struct omap_hwmod_ocp_if
omap3xxx_l3_main__l4_per = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* L3 taret configuration and error log registers */ static struct
+omap_hwmod_irq_info omap3xxx_l3_targ_irqs[] = {
+ { .irq = INT_34XX_L3_DBG_IRQ },
+ { .irq = INT_34XX_L3_APP_IRQ },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_l3_targ_addrs[] = {
+ {
+ .pa_start = 0x68000000,
+ .pa_end = 0x68100000,
+ .flags = ADDR_TYPE_RT,
+ },
+};
+
/* MPU -> L3 interface */
static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
- .master = &omap3xxx_mpu_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
+ .master = &omap3xxx_mpu_hwmod,
+ .slave = &omap3xxx_l3_main_hwmod,
+ .addr = omap3xxx_l3_targ_addrs,
+ .addr_cnt = ARRAY_SIZE(omap3xxx_l3_targ_addrs),
.user = OCP_USER_MPU,
};
@@ -94,6 +110,8 @@ static struct omap_hwmod_ocp_if
*omap3xxx_l3_main_masters[] = { static struct omap_hwmod
omap3xxx_l3_main_hwmod = {
.name = "l3_main",
.class = &l3_hwmod_class,
+ .mpu_irqs = omap3xxx_l3_targ_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_targ_irqs),
.masters = omap3xxx_l3_main_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
.slaves = omap3xxx_l3_main_slaves,
b/arch/arm/plat-omap/include/plat/irqs.h
@@ -315,6 +315,8 @@
#define INT_34XX_SSM_ABORT_IRQ 6
#define INT_34XX_SYS_NIRQ 7
#define INT_34XX_D2D_FW_IRQ 8
+#define INT_34XX_L3_DBG_IRQ 9
+#define INT_34XX_L3_APP_IRQ 10
#define INT_34XX_PRCM_MPU_IRQ 11
#define INT_34XX_MCBSP1_IRQ 16
#define INT_34XX_MCBSP2_IRQ 17