From patchwork Mon Dec 14 09:47:15 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vimal singh X-Patchwork-Id: 67231 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nBE9mXVh022600 for ; Mon, 14 Dec 2009 09:48:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755388AbZLNJrs (ORCPT ); Mon, 14 Dec 2009 04:47:48 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755311AbZLNJrl (ORCPT ); Mon, 14 Dec 2009 04:47:41 -0500 Received: from mail-bw0-f227.google.com ([209.85.218.227]:56176 "EHLO mail-bw0-f227.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754458AbZLNJrh (ORCPT ); Mon, 14 Dec 2009 04:47:37 -0500 Received: by bwz27 with SMTP id 27so1843210bwz.21 for ; Mon, 14 Dec 2009 01:47:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :from:date:message-id:subject:to:cc:content-type; bh=cOGB49iQGz3Sgmn9NHlvTZ7q4FrAUwaDViMsXn7vmFw=; b=ZeiRC+oAQeaBXrW7Nv5vmf0D6r+PHBFDh8y6E0AGudL/um0bkeo3X7lt+bxPNPDBFP JvbLZWJYh8ATwCk+SSs8ofA+gjphGS7WllOh36Awf6V0tc/TgfKeB3I5ynk/4U2OpSM8 0ZDUP4OsNdyW3UilljcKENm4swHQJDtgg6fos= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; b=M9PTPB+jHgorY1J/pXIccKOW2U083ARtr+ZjCTLTRTfX/QjQevncmbIIVo3vAtQVoJ 0nuE4Le3/VUNegQl1qA8dugh08Z2TtELgCEVikD5IYAPbgNlHUh3/Szrg7DMwLq5Oial R9YweoePBEH+M2cXUaMELo89Eh5OL/RU+VuGI= MIME-Version: 1.0 Received: by 10.204.25.81 with SMTP id y17mr2680400bkb.96.1260784055198; Mon, 14 Dec 2009 01:47:35 -0800 (PST) In-Reply-To: References: <64662.192.168.10.89.1259933932.squirrel@dbdmail.itg.ti.com> <20091204220138.GJ24013@atomide.com> <20091207175644.GA24013@atomide.com> <20091208235725.GA24013@atomide.com> From: Vimal Singh Date: Mon, 14 Dec 2009 15:17:15 +0530 Message-ID: Subject: [PATCH v2 2/2]: Introducing 'gpmc-nand.c' for GPMC specific NAND init To: Tony Lindgren Cc: "Govindraj.R" , linux-omap@vger.kernel.org, Linux MTD Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 59b0ccc..0dfe27a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -103,5 +103,8 @@ obj-y += usb-ehci.o onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o obj-y += $(onenand-m) $(onenand-y) +nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o +obj-y += $(nand-m) $(nand-y) + smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c new file mode 100644 index 0000000..c0e8ba7 --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -0,0 +1,137 @@ +/* + * gpmc-nand.c + * + * Copyright (C) 2009 Texas Instruments + * Vimal Singh + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include +#include +#include + +#define WR_RD_PIN_MONITORING 0x00600000 +#define MASKADDR 8 + +static struct omap_nand_platform_data *gpmc_nand_data; + +static struct resource gpmc_nand_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device gpmc_nand_device = { + .name = "omap2-nand", + .id = 0, + .num_resources = 1, + .resource = &gpmc_nand_resource, +}; + +static int omap2_nand_gpmc_config(int cs, void __iomem *nand_base) +{ + struct gpmc_timings t; + int err; + + const int cs_rd_off = 36; + const int cs_wr_off = 36; + const int adv_on = 6; + const int adv_rd_off = 24; + const int adv_wr_off = 36; + const int oe_off = 48; + const int we_off = 30; + const int rd_cycle = 72; + const int wr_cycle = 72; + const int access = 54; + const int wr_data_mux_bus = 0; + const int wr_access = 30; + + memset(&t, 0, sizeof(t)); + t.sync_clk = 0; + t.cs_on = 0; + t.adv_on = gpmc_round_ns_to_ticks(adv_on); + + /* Read */ + t.adv_rd_off = gpmc_round_ns_to_ticks(adv_rd_off); + t.oe_on = t.adv_on; + t.access = gpmc_round_ns_to_ticks(access); + t.oe_off = gpmc_round_ns_to_ticks(oe_off); + t.cs_rd_off = gpmc_round_ns_to_ticks(cs_rd_off); + t.rd_cycle = gpmc_round_ns_to_ticks(rd_cycle); + + /* Write */ + t.adv_wr_off = gpmc_round_ns_to_ticks(adv_wr_off); + t.we_on = t.oe_on; + if (cpu_is_omap34xx()) { + t.wr_data_mux_bus = gpmc_round_ns_to_ticks(wr_data_mux_bus); + t.wr_access = gpmc_round_ns_to_ticks(wr_access); + } + t.we_off = gpmc_round_ns_to_ticks(we_off); + t.cs_wr_off = gpmc_round_ns_to_ticks(cs_wr_off); + t.wr_cycle = gpmc_round_ns_to_ticks(wr_cycle); + + /* Configure GPMC */ + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, + GPMC_CONFIG1_DEVICESIZE(gpmc_nand_data->devsize) | + GPMC_CONFIG1_DEVICETYPE_NAND); + + err = gpmc_cs_set_timings(cs, &t); + if (err) + return err; + + return 0; +} + +static int gpmc_nand_setup(void __iomem *nand_base) +{ + struct device *dev = &gpmc_nand_device.dev; + + /* Set timings in GPMC */ + if (omap2_nand_gpmc_config(gpmc_nand_data->cs, nand_base) < 0) { + dev_err(dev, "Unable to set gpmc timings\n"); + return -EINVAL; + } + + return 0; +} + +int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data) +{ + unsigned int val; + int err = 0; + struct device *dev = &gpmc_nand_device.dev; + + gpmc_nand_data = _nand_data; + gpmc_nand_data->nand_setup = gpmc_nand_setup; + gpmc_nand_device.dev.platform_data = gpmc_nand_data; + + err = gpmc_nand_setup(gpmc_nand_data->gpmc_cs_baseaddr); + if (err < 0) { + dev_err(dev, "NAND platform setup failed: %d\n", err); + return err; + } + + /* Enable RD PIN Monitoring Reg */ + if (gpmc_nand_data->dev_ready) { + val = gpmc_cs_read_reg(gpmc_nand_data->cs, + GPMC_CS_CONFIG1); + val |= WR_RD_PIN_MONITORING; + gpmc_cs_write_reg(gpmc_nand_data->cs, + GPMC_CS_CONFIG1, val); + } + + err = platform_device_register(&gpmc_nand_device); + if (err < 0) { + dev_err(dev, "Unable to register NAND device\n"); + return err; + } + + return 0; +} diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h index 631a7be..2ba9842 100644 --- a/arch/arm/plat-omap/include/plat/nand.h +++ b/arch/arm/plat-omap/include/plat/nand.h @@ -21,4 +21,10 @@ struct omap_nand_platform_data { int dma_channel; void __iomem *gpmc_cs_baseaddr; void __iomem *gpmc_baseaddr; + int devsize; }; + +/* size (4 KiB) for IO mapping */ +#define NAND_IO_SIZE SZ_4K + +extern int gpmc_nand_init(struct omap_nand_platform_data *d); diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 1bb799f..aaef170 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -30,12 +30,8 @@ #define DRIVER_NAME "omap2-nand" -/* size (4 KiB) for IO mapping */ -#define NAND_IO_SIZE SZ_4K - #define NAND_WP_OFF 0 #define NAND_WP_BIT 0x00000010 -#define WR_RD_PIN_MONITORING 0x00600000 #define GPMC_BUF_FULL 0x00000001 #define GPMC_BUF_EMPTY 0x00000000 @@ -882,8 +878,6 @@ static int __devinit omap_nand_probe struct omap_nand_info *info; struct omap_nand_platform_data *pdata; int err; - unsigned long val; - pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -910,24 +904,15 @@ static int __devinit omap_nand_probe info->mtd.name = dev_name(&pdev->dev); info->mtd.owner = THIS_MODULE; + info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0; + info->nand.options |= NAND_SKIP_BBTSCAN; + err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base); if (err < 0) { dev_err(&pdev->dev, "Cannot request GPMC CS\n"); goto out_free_info; } - /* Enable RD PIN Monitoring Reg */ - if (pdata->dev_ready) { - val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1); - val |= WR_RD_PIN_MONITORING; - gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val); - } - - val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7); - val &= ~(0xf << 8); - val |= (0xc & 0xf) << 8; - gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val); - /* NAND write protect off */ omap_nand_wp(&info->mtd, NAND_WP_OFF); @@ -963,11 +948,6 @@ static int __devinit omap_nand_probe info->nand.chip_delay = 50; } - info->nand.options |= NAND_SKIP_BBTSCAN; - if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000) - == 0x1000) - info->nand.options |= NAND_BUSWIDTH_16; - if (use_prefetch) { /* copy the virtual address of nand base for fifo access */ info->nand_pref_fifo_add = info->nand.IO_ADDR_R;