From patchwork Fri Aug 2 13:36:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Afzal Mohammed X-Patchwork-Id: 2837898 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 27A8ABF535 for ; Fri, 2 Aug 2013 13:37:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CDB442048E for ; Fri, 2 Aug 2013 13:37:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 96B1D20489 for ; Fri, 2 Aug 2013 13:37:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752649Ab3HBNhQ (ORCPT ); Fri, 2 Aug 2013 09:37:16 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:41211 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752607Ab3HBNhP (ORCPT ); Fri, 2 Aug 2013 09:37:15 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r72Daeon017171; Fri, 2 Aug 2013 08:36:40 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r72DaeM5013734; Fri, 2 Aug 2013 08:36:40 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Fri, 2 Aug 2013 08:36:40 -0500 Received: from afzal-Latitude-E6420.india.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r72DaZZe009367; Fri, 2 Aug 2013 08:36:37 -0500 From: Afzal Mohammed To: , CC: Tony Lindgren , Paul Walmsley , Benoit Cousson , , Vaibhav Bedia Subject: [PATCH v2 01/13] ARM: OMAP2+: CM: reintroduce SW_SLEEP for OMAP4 Date: Fri, 2 Aug 2013 19:06:35 +0530 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vaibhav Bedia "65aa94b ARM: OMAP4: clockdomain/CM code: Update supported transition modes" removed SW_SLEEP mode for clockdomains on OMAP4 class of devices. Not having SW_SLEEP mode works fine for OMAP4/5 devices but it gets in the way of reuse for other devices like AM43x which have the same hardware but where most of clockdomains support only SW_SLEEP/SW_WKUP modes. This also can help make AM335x (which has custom functions) reuse OMAP4 PRM/CM functions. While here also fixup a trivial typo in the comment. [afzal@ti.com: Alter message to refer to AM43x instead of AM335x, this was pulled in from series that reuses OMAP4 PRM/CM for AM335x, which as of now is not being followed upon] Signed-off-by: Vaibhav Bedia Signed-off-by: Afzal Mohammed --- arch/arm/mach-omap2/cminst44xx.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index f0290f5..35051fd 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -237,7 +237,7 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) } /** - * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle + * omap4_cminst_clkdm_force_wakeup - try to take a clockdomain out of idle * @part: PRCM partition ID that the clockdomain registers exist in * @inst: CM instance register offset (*_INST macro) * @cdoffs: Clockdomain register offset (*_CDOFFS macro) @@ -250,6 +250,20 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); } +/** + * omap4_cminst_clkdm_force_sleep - try to put a clockdomain to idle + * @part: PRCM partition ID that the clockdomain registers exist in + * @inst: CM instance register offset (*_INST macro) + * @cdoffs: Clockdomain register offset (*_CDOFFS macro) + * + * Put a clockdomain referred to by (@part, @inst, @cdoffs) to idle, + * forcing it to sleep. No return value. + */ +void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); +} + /* * */ @@ -404,8 +418,8 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) static int omap4_clkdm_sleep(struct clockdomain *clkdm) { - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, clkdm->clkdm_offs); + omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, + clkdm->cm_inst, clkdm->clkdm_offs); return 0; }