From patchwork Thu Apr 8 13:42:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Sakoman X-Patchwork-Id: 91273 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o38DgHdm012997 for ; Thu, 8 Apr 2010 13:42:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758608Ab0DHNmP (ORCPT ); Thu, 8 Apr 2010 09:42:15 -0400 Received: from mail-qy0-f179.google.com ([209.85.221.179]:40137 "EHLO mail-qy0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758468Ab0DHNmO (ORCPT ); Thu, 8 Apr 2010 09:42:14 -0400 Received: by qyk9 with SMTP id 9so104409qyk.1 for ; Thu, 08 Apr 2010 06:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:received:message-id :subject:from:to:content-type; bh=rDlwHcio685hE/aSj6oBVhPeHujdRrjAjEu+bm8L5CI=; b=K/j2Qs15jEO+XLY5sCjLTmfGOZQeUP0xuYaFXwAU3YEvl97GVnWxTkY1f5aVXToaCz vJhqcf0nq3JY7sFOCW5Nhetlxh6YRYMtqFs/aL8FS2uDHwgQNpsnqBtjJgaFf1eb1Nd9 96OPhbkS4RImCAjv3BWI5U6TR/4e5EBjeh4o0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=q/KttJrXScrNUQl2NJUpsyR6UBBSu6UcVPe5PrY1Aax2KRwcQ5eX3R4gGGfVZJbDkj 5Uaf7j5ANe7JGFxJEaEL3oyyrl1N3KR9lZ1NYTxU4Z07CnNPzXtv3ZBUzRSfzaHt/67K AV2sMaoXtElUfcpnb/s37JYYxhVAhzmSLlVk0= MIME-Version: 1.0 Received: by 10.229.70.133 with HTTP; Thu, 8 Apr 2010 06:42:12 -0700 (PDT) Date: Thu, 8 Apr 2010 06:42:12 -0700 Received: by 10.229.192.68 with SMTP id dp4mr236751qcb.36.1270734132605; Thu, 08 Apr 2010 06:42:12 -0700 (PDT) Message-ID: Subject: [PATCHv2] ARM: OMAP: Overo: use new gpmc nand infrastructure From: Steve Sakoman To: linux-omap@vger.kernel.org Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 08 Apr 2010 13:42:18 +0000 (UTC) diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 8848c7c..ae23633 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -184,6 +184,11 @@ static inline void __init overo_init_smsc911x(void) static inline void __init overo_init_smsc911x(void) { return; } #endif +struct flash_partitions { + struct mtd_partition *parts; + int nr_parts; +}; + static struct mtd_partition overo_nand_partitions[] = { { .name = "xloader", @@ -213,34 +218,80 @@ static struct mtd_partition overo_nand_partitions[] = { }, }; -static struct omap_nand_platform_data overo_nand_data = { - .parts = overo_nand_partitions, - .nr_parts = ARRAY_SIZE(overo_nand_partitions), - .dma_channel = -1, /* disable DMA in OMAP NAND driver */ +static struct flash_partitions overo_flash_partitions[] = { + { + /* NOR flash */ + }, + { + /* OneNAND */ + }, + { + /* NAND */ + .parts = overo_nand_partitions, + .nr_parts = ARRAY_SIZE(overo_nand_partitions), + }, }; -static struct resource overo_nand_resource = { - .flags = IORESOURCE_MEM, +#if defined(CONFIG_MTD_NAND_OMAP2) || \ + defined(CONFIG_MTD_NAND_OMAP2_MODULE) + +/* Note that all values in this struct are in nanoseconds */ +static struct gpmc_timings nand_timings = { + + .sync_clk = 0, + + .cs_on = 0, + .cs_rd_off = 36, + .cs_wr_off = 36, + + .adv_on = 6, + .adv_rd_off = 24, + .adv_wr_off = 36, + + .we_off = 30, + .oe_off = 48, + + .access = 54, + .rd_cycle = 72, + .wr_cycle = 72, + + .wr_access = 30, + .wr_data_mux_bus = 0, }; -static struct platform_device overo_nand_device = { - .name = "omap2-nand", - .id = -1, - .dev = { - .platform_data = &overo_nand_data, - }, - .num_resources = 1, - .resource = &overo_nand_resource, +static struct omap_nand_platform_data overo_nand_data = { + .nand_setup = NULL, + .gpmc_t = &nand_timings, + .dma_channel = -1, /* disable DMA in OMAP NAND driver */ + .dev_ready = NULL, + .devsize = 1, /* '0' for 8-bit, '1' for 16-bit device */ }; +static void +__init board_nand_init(struct flash_partitions overo_nand_parts, u8 cs) +{ + overo_nand_data.cs = cs; + overo_nand_data.parts = overo_nand_parts.parts; + overo_nand_data.nr_parts = overo_nand_parts.nr_parts; + overo_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT); + + overo_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT + + GPMC_CS0_BASE + cs * GPMC_CS_SIZE); -static void __init overo_flash_init(void) + gpmc_nand_init(&overo_nand_data); +} +#else +static void +__init board_nand_init(struct flash_partitions overo_nand_parts, u8 cs) { +} +#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ + +static void +__init overo_flash_init(struct flash_partitions partition_info[]) { u8 cs = 0; u8 nandcs = GPMC_CS_NUM + 1; - u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; - /* find out the chip-select on which NAND exists */ while (cs < GPMC_CS_NUM) { u32 ret = 0; @@ -260,16 +311,8 @@ static void __init overo_flash_init(void) return; } - if (nandcs < GPMC_CS_NUM) { - overo_nand_data.cs = nandcs; - overo_nand_data.gpmc_cs_baseaddr = (void *) - (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE); - overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add); - - printk(KERN_INFO "Registering NAND on CS%d\n", nandcs); - if (platform_device_register(&overo_nand_device) < 0) - printk(KERN_ERR "Unable to register NAND device\n"); - } + if (nandcs < GPMC_CS_NUM) + board_nand_init(partition_info[2], nandcs); } static struct omap2_hsmmc_info mmc[] = { @@ -425,7 +468,7 @@ static void __init overo_init(void) overo_i2c_init(); platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); omap_serial_init(); - overo_flash_init(); + overo_flash_init(overo_flash_partitions); usb_musb_init(&musb_board_data); usb_ehci_init(&ehci_pdata); overo_ads7846_init();