PCI patch breaks boot on rp2470 (2xPA8700)

Commit Message

Carlos O'Donell Feb. 22, 2010, 11:25 p.m. UTC

None

Patch

Subject: [PATCH] hppa: Set PCI CLS early in boot.
From: Carlos O'Donell <[e-mail]>

Set the PCI CLS early in the boot process to prevent
device failures. In pcibios_set_master use the new 
pci_cache_line_size instead of a hard-coded value.

Signed-off-by: Carlos O'Donell <[e-mail]>

---
 arch/parisc/kernel/pci.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index f7064ab..4f84991 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -18,7 +18,6 @@ 
 
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/cache.h>		/* for L1_CACHE_BYTES */
 #include <asm/superio.h>
 
 #define DEBUG_RESOURCES 0
@@ -123,6 +122,10 @@  static int __init pcibios_init(void)
 	} else {
 		printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
 	}
+
+	/* Set the CLS for PCI as early as possible. */
+	pci_cache_line_size = pci_dfl_cache_line_size;
+ 
 	return 0;
 }
 
@@ -170,8 +173,8 @@  void pcibios_set_master(struct pci_dev *dev)
 	** HP generally has fewer devices on the bus than other architectures.
 	** upper byte is PCI_LATENCY_TIMER.
 	*/
-	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
-				(0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
+	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 
+			      (0x80 << 8) | pci_cache_line_size);
 }