From patchwork Thu Dec 2 23:36:47 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Bottomley X-Patchwork-Id: 376171 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB2Naqeo005243 for ; Thu, 2 Dec 2010 23:36:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757651Ab0LBXgw (ORCPT ); Thu, 2 Dec 2010 18:36:52 -0500 Received: from bedivere.hansenpartnership.com ([66.63.167.143]:59301 "EHLO bedivere.hansenpartnership.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756216Ab0LBXgv (ORCPT ); Thu, 2 Dec 2010 18:36:51 -0500 Received: from localhost (localhost [127.0.0.1]) by bedivere.hansenpartnership.com (Postfix) with ESMTP id 8C9D58EE0F8 for ; Thu, 2 Dec 2010 15:36:49 -0800 (PST) Received: from bedivere.hansenpartnership.com ([127.0.0.1]) by localhost (bedivere.hansenpartnership.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ttq99Pe8rWZ7 for ; Thu, 2 Dec 2010 15:36:49 -0800 (PST) Received: from [192.168.2.10] (dagonet.hansenpartnership.com [76.243.235.53]) by bedivere.hansenpartnership.com (Postfix) with ESMTPSA id 3ACB98EE0E2 for ; Thu, 2 Dec 2010 15:36:49 -0800 (PST) Subject: [PATCH] parisc: fix dino/gsc interrupts From: James Bottomley To: linux-parisc@vger.kernel.org Date: Thu, 02 Dec 2010 17:36:47 -0600 Message-ID: <1291333007.19250.10.camel@mulgrave.site> Mime-Version: 1.0 X-Mailer: Evolution 2.30.1.2 Sender: linux-parisc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 02 Dec 2010 23:36:52 +0000 (UTC) diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index 5024f64..48aa711 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -392,7 +392,7 @@ static void claim_cpu_irqs(void) int i; for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { set_irq_chip_and_handler(i, &cpu_interrupt_type, - handle_level_irq); + handle_percpu_irq); } set_irq_handler(TIMER_IRQ, handle_percpu_irq);