@@ -104,16 +104,6 @@ static void (*interrupt[NR_IRQS])(void) = {
IRQ31_interrupt
};
-static void enable_crisv10_irq(unsigned int irq);
-
-static unsigned int startup_crisv10_irq(unsigned int irq)
-{
- enable_crisv10_irq(irq);
- return 0;
-}
-
-#define shutdown_crisv10_irq disable_crisv10_irq
-
static void enable_crisv10_irq(unsigned int irq)
{
crisv10_unmask_irq(irq);
@@ -124,22 +114,16 @@ static void disable_crisv10_irq(unsigned int irq)
crisv10_mask_irq(irq);
}
-static void ack_crisv10_irq(unsigned int irq)
-{
-}
-
-static void end_crisv10_irq(unsigned int irq)
+static void crisv10_noop(unsigned int irq)
{
}
static struct irq_chip crisv10_irq_type = {
.name = "CRISv10",
- .startup = startup_crisv10_irq,
- .shutdown = shutdown_crisv10_irq,
- .enable = enable_crisv10_irq,
+ .unmask = enable_crisv10_irq,
+ .mask = disable_crisv10_irq,
.disable = disable_crisv10_irq,
- .ack = ack_crisv10_irq,
- .end = end_crisv10_irq,
+ .ack = crisv10_noop,
.set_affinity = NULL
};
@@ -221,7 +205,7 @@ init_IRQ(void)
/* Initialize IRQ handler descriptors. */
for(i = 2; i < NR_IRQS; i++) {
- irq_desc[i].chip = &crisv10_irq_type;
+ set_irq_chip_and_handler(i, &crisv10_irq_type, handle_simple_irq);
set_int_vector(i, interrupt[i]);
}
@@ -290,36 +290,6 @@ void crisv32_unmask_irq(int irq)
unblock_irq(irq, irq_cpu(irq));
}
-
-static unsigned int startup_crisv32_irq(unsigned int irq)
-{
- crisv32_unmask_irq(irq);
- return 0;
-}
-
-static void shutdown_crisv32_irq(unsigned int irq)
-{
- crisv32_mask_irq(irq);
-}
-
-static void enable_crisv32_irq(unsigned int irq)
-{
- crisv32_unmask_irq(irq);
-}
-
-static void disable_crisv32_irq(unsigned int irq)
-{
- crisv32_mask_irq(irq);
-}
-
-static void ack_crisv32_irq(unsigned int irq)
-{
-}
-
-static void end_crisv32_irq(unsigned int irq)
-{
-}
-
int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest)
{
unsigned long flags;
@@ -330,14 +300,16 @@ int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest)
return 0;
}
+static void crisv32_noop(unsigned int irq)
+{
+}
+
static struct irq_chip crisv32_irq_type = {
.name = "CRISv32",
- .startup = startup_crisv32_irq,
- .shutdown = shutdown_crisv32_irq,
- .enable = enable_crisv32_irq,
- .disable = disable_crisv32_irq,
- .ack = ack_crisv32_irq,
- .end = end_crisv32_irq,
+ .mask = crisv32_mask_irq,
+ .disable = crisv32_mask_irq,
+ .unmask = crisv32_unmask_irq,
+ .ack = crisv32_noop,
.set_affinity = set_affinity_crisv32_irq
};
@@ -472,15 +444,18 @@ init_IRQ(void)
/* Point all IRQ's to bad handlers. */
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
- irq_desc[j].chip = &crisv32_irq_type;
+ set_irq_chip_and_handler(j, &crisv32_irq_type,
+ handle_simple_irq);
set_exception_vector(i, interrupt[j]);
}
/* Mark Timer and IPI IRQs as CPU local */
irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
irq_desc[TIMER0_INTR_VECT].status |= IRQ_PER_CPU;
+ set_irq_handler(TIMER0_INTR_VECT, handle_percpu_irq);
irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
irq_desc[IPI_INTR_VECT].status |= IRQ_PER_CPU;
+ set_irq_handler(IPI_INTR_VECT, handle_percpu_irq);
set_exception_vector(0x00, nmi_interrupt);
set_exception_vector(0x30, multiple_interrupt);
@@ -93,7 +93,7 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
printk("do_IRQ: stack overflow: %lX\n", sp);
show_stack(NULL, (unsigned long *)sp);
}
- __do_IRQ(irq);
+ generic_handle_irq(irq);
irq_exit();
set_irq_regs(old_regs);
}