@@ -1026,18 +1026,15 @@ static int emit_load_r64(const s8 *dst, const s8 *src, s16 off,
switch (size) {
case BPF_B:
emit(hppa_ldb(off + 0, srcreg, lo(rd)), ctx);
- if (!ctx->prog->aux->verifier_zext)
- emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
+ emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
break;
case BPF_H:
emit(hppa_ldh(off + 0, srcreg, lo(rd)), ctx);
- if (!ctx->prog->aux->verifier_zext)
- emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
+ emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
break;
case BPF_W:
emit(hppa_ldw(off + 0, srcreg, lo(rd)), ctx);
- if (!ctx->prog->aux->verifier_zext)
- emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
+ emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
break;
case BPF_DW:
emit(hppa_ldw(off + 0, srcreg, hi(rd)), ctx);
The JITs should not depend on the verifier for zero extending the upper 32 bits of the destination register when loading a byte, half-word, or word. A following patch will make the verifier stop patching zext instructions after LDX. Signed-off-by: Puranjay Mohan <puranjay12@gmail.com> --- arch/parisc/net/bpf_jit_comp32.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)