diff mbox

[v3] parisc: Change L1_CACHE_BYTES to 16

Message ID B8E85737-5ECD-4CBE-8730-886B098C5FA4@bell.net (mailing list archive)
State Superseded
Headers show

Commit Message

John David Anglin Oct. 15, 2015, 12:32 a.m. UTC
The latest version changes L1_CACHE_BYTES to 16 bytes and doesn't adjust SMP_CACHE_BYTES as
per James suggestion

Tested for 16 days on rp3440.

Signed-off-by: John David Anglin <dave.anglin@bell.net>

--
John David Anglin	dave.anglin@bell.net

Comments

Helge Deller Oct. 22, 2015, 11:38 a.m. UTC | #1
> Betreff: [PATCH v3] parisc: Change L1_CACHE_BYTES to 16
> The latest version changes L1_CACHE_BYTES to 16 bytes and doesn't adjust SMP_CACHE_BYTES as
> per James suggestion

This patch sadly breaks build on Linux kernel git head:

In file included from /home/cvs/LINUX/git-kernel/linux-2.6/net/core/dev.c:92:0:
/net/core/dev.c: In function ‘expand_xps_map’:
/include/linux/netdevice.h:721:27: warning: overflow in implicit constant conversion [-Woverflow]
 #define XPS_MIN_MAP_ALLOC ((L1_CACHE_BYTES - sizeof(struct xps_map)) \
/net/core/dev.c:1972:18: note: in expansion of macro ‘XPS_MIN_MAP_ALLOC’
  int alloc_len = XPS_MIN_MAP_ALLOC;
                  ^
Helge
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diff mbox

Patch

diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 47f11c7..3d0e17b 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -7,20 +7,12 @@ 
 
 
 /*
- * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
- * 32-byte cachelines.  The default configuration is not for SMP anyway,
- * so if you're building for SMP, you should select the appropriate
- * processor type.  There is a potential livelock danger when running
- * a machine with this value set too small, but it's more probable you'll
- * just ruin performance.
+ * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
+ * have 32-byte cachelines.  The L1 length appears to be 16 bytes but this
+ * is not clearly documented.
  */
-#ifdef CONFIG_PA20
-#define L1_CACHE_BYTES 64
-#define L1_CACHE_SHIFT 6
-#else
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-#endif
+#define L1_CACHE_BYTES 16
+#define L1_CACHE_SHIFT 4
 
 #ifndef __ASSEMBLY__