From patchwork Thu Oct 15 00:32:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 7399291 Return-Path: X-Original-To: patchwork-linux-parisc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B12209F37F for ; Thu, 15 Oct 2015 00:32:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 17DF2207B5 for ; Thu, 15 Oct 2015 00:32:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EDB5C2078D for ; Thu, 15 Oct 2015 00:32:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752291AbbJOAcO (ORCPT ); Wed, 14 Oct 2015 20:32:14 -0400 Received: from simcoe208srvr.owm.bell.net ([184.150.200.208]:30723 "EHLO torfep02.bell.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751098AbbJOAcO (ORCPT ); Wed, 14 Oct 2015 20:32:14 -0400 Received: from bell.net torfep02 184.150.200.158 by torfep02.bell.net with ESMTP id <20151015003212.JLRK19496.torfep02.bell.net@torspm01.bell.net> for ; Wed, 14 Oct 2015 20:32:12 -0400 Received: from [192.168.2.10] (really [76.69.120.10]) by torspm01.bell.net with ESMTP id <20151015003212.FNRY24849.torspm01.bell.net@[192.168.2.10]>; Wed, 14 Oct 2015 20:32:12 -0400 Subject: [PATCH v3] parisc: Change L1_CACHE_BYTES to 16 Mime-Version: 1.0 (Apple Message framework v1085) From: John David Anglin In-Reply-To: <32A3BF6F-B243-4AD4-9AE9-A5F9DAE0270A@bell.net> Date: Wed, 14 Oct 2015 20:32:11 -0400 Cc: linux-parisc List , Helge Deller , James Bottomley Message-Id: References: <42430464-867C-4E0B-8E95-C6CDB6D8A0B2@bell.net> <32A3BF6F-B243-4AD4-9AE9-A5F9DAE0270A@bell.net> To: John David Anglin X-Mailer: Apple Mail (2.1085) X-Opwv-CommTouchExtSvcRefID: str=0001.0A020206.561EF40C.00B6, ss=1, re=0.000, fgs=0 Sender: linux-parisc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The latest version changes L1_CACHE_BYTES to 16 bytes and doesn't adjust SMP_CACHE_BYTES as per James suggestion Tested for 16 days on rp3440. Signed-off-by: John David Anglin --- John David Anglin dave.anglin@bell.net diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 47f11c7..3d0e17b 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -7,20 +7,12 @@ /* - * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have - * 32-byte cachelines. The default configuration is not for SMP anyway, - * so if you're building for SMP, you should select the appropriate - * processor type. There is a potential livelock danger when running - * a machine with this value set too small, but it's more probable you'll - * just ruin performance. + * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors + * have 32-byte cachelines. The L1 length appears to be 16 bytes but this + * is not clearly documented. */ -#ifdef CONFIG_PA20 -#define L1_CACHE_BYTES 64 -#define L1_CACHE_SHIFT 6 -#else -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 -#endif +#define L1_CACHE_BYTES 16 +#define L1_CACHE_SHIFT 4 #ifndef __ASSEMBLY__