From patchwork Fri Dec 7 00:53:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 10717285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BADA713BB for ; Fri, 7 Dec 2018 00:53:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ABB352EEEB for ; Fri, 7 Dec 2018 00:53:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9D5252EEDB; Fri, 7 Dec 2018 00:53:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 561F12EEDB for ; Fri, 7 Dec 2018 00:53:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725963AbeLGAxT (ORCPT ); Thu, 6 Dec 2018 19:53:19 -0500 Received: from mx.socionext.com ([202.248.49.38]:42321 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725950AbeLGAxT (ORCPT ); Thu, 6 Dec 2018 19:53:19 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 07 Dec 2018 09:53:17 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 6104660062; Fri, 7 Dec 2018 09:53:17 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Dec 2018 09:53:17 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id F34C41A1235; Fri, 7 Dec 2018 09:53:16 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Gustavo Pimentel , Kunihiko Hayashi Subject: [PATCH v5 0/2] Add new UniPhier PCIe host driver Date: Fri, 7 Dec 2018 09:53:10 +0900 Message-Id: <1544143992-16385-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This series adds PCIe host controller driver for Socionext UniPhier SoCs. This controller is based on the DesignWare PCIe core. This driver supports LD20 and PXs3 SoCs. v4: https://www.spinics.net/lists/linux-pci/msg78278.html About legacy IRQ, it might be necessary to share common view from keystone driver that have been cleaned up[1]. [1] https://lore.kernel.org/patchwork/patch/989541/ Changes since v4: - fix an issue of using the wrong value to mask IRQ mask register Changes since v3: - dt-bindings: fix INTX numbering of legacy interrupt map - change interrupts to level ones - remove .xlate function - merge uniphier_pcie_ltssm_disable() into uniphier_pcie_ltssm_enable() - remove an error message on uniphier_pcie_establish_link() - change the order between irq_domain_add_liniear() and irq_set_chained_handler_and_data() - replace dummy_irq_chip with uniphier_pcie_irq_chip and its functions - add dependency on CONFIG_HAS_IOMEM - MAINTAINERS: add pcie-uniphier entry Changes since v2: - dt-bindings: remove a comment that the node name isn't important - dt-bindings: remove "intx" interrupt - dt-bindings: define 'legacy-interrupt-controller' node and its properties - return an error value when link up fails - remove devm_request_irq() and a handler for MSI IRQ - use chained interrupt instead of devm_request_irq() for legacy IRQ - add unipher_pcie_config_legacy_irq() to get legacy IRQ from 'legacy-interrupt controller' node - replace 4 statments to handle INTX with for_each_set_bit() - remove initialization of pp->root_bus_nr - remove indivisual interrupt enable bit definitions - rename 'irq_domain' member to 'legacy_irq_domain' in private structure - use pci_irqd_intx_xlate() for irq_domain_ops.xlate function Changes since v1: - follow capitalization conventions in the descriptions - use C style comments except for the SPDX line Kunihiko Hayashi (2): dt-bindings: PCI: Add UniPhier PCIe host controller description PCI: uniphier: Add UniPhier PCIe host controller support .../devicetree/bindings/pci/uniphier-pcie.txt | 81 ++++ MAINTAINERS | 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-uniphier.c | 471 +++++++++++++++++++++ 5 files changed, 570 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie.txt create mode 100644 drivers/pci/controller/dwc/pcie-uniphier.c