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[v5,0/3] Add Stratix 10 PCIe Root Port support

Message ID 1551172548-36344-1-git-send-email-ley.foon.tan@intel.com (mailing list archive)
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Series Add Stratix 10 PCIe Root Port support | expand

Message

Tan, Ley Foon Feb. 26, 2019, 9:15 a.m. UTC 
Add PCIe Root Port support for Stratix 10 device and also update
device tree binding documentation.

v4 -> v5:
---------
- Add struct altera_pcie_ops
- Add count checking in s10_tlp_read_packet()

v3 -> v4:
---------
- Separate Kconfig change to a patch
- Change cast to mask

v2 -> v3:
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- Rename Stratix10 to Stratix 10.
- Change bool s10_flag to enum version.

v1 -> v2:
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- Add define S10_TLP_FMTTYPE_* macros.
- Remove initialize structure members to NULL/zero.
- Rename *_funcs to *_data.
- Update comment and fix coding style warning from checkpatch.pl.
- Rename StratixXX to stratix10.

History:
--------
[v1]: https://lkml.org/lkml/2018/12/26/68
[v2]: https://lkml.org/lkml/2018/12/31/46
[v3]: https://lkml.org/lkml/2019/1/2/16
[v4]: https://lkml.org/lkml/2019/2/14/58

Ley Foon Tan (3):
  PCI: altera: Add Stratix 10 PCIe support
  PCI: altera: Enable driver on ARM64
  dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0

 .../devicetree/bindings/pci/altera-pcie.txt   |   4 +-
 drivers/pci/controller/Kconfig                |   2 +-
 drivers/pci/controller/pcie-altera.c          | 266 ++++++++++++++++--
 3 files changed, 246 insertions(+), 26 deletions(-)