| Message ID | 1618241456-27200-1-git-send-email-bpeled@marvell.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Asynchronous linkdown recovery | expand |
Hi all, Please ignore this patch list there is a small change missing. -----Original Message----- From: bpeled@marvell.com <bpeled@marvell.com> Sent: Monday, April 12, 2021 6:31 PM To: thomas.petazzoni@bootlin.com; lorenzo.pieralisi@arm.com; bhelgaas@google.com Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-pci@vger.kernel.org; sebastian.hesselbarth@gmail.com; gregory.clement@bootlin.com; andrew@lunn.ch; robh+dt@kernel.org; mw@semihalf.com; jaz@semihalf.com; Kostya Porotchkin <kostap@marvell.com>; Nadav Haklai <nadavh@marvell.com>; Stefan Chulski <stefanc@marvell.com>; Ofer Heifetz <oferh@marvell.com>; Ben Peled <bpeled@marvell.com> Subject: [”PATCH” 0/5] Asynchronous linkdown recovery From: Ben Peled <bpeled@marvell.com> The following patches implement the required procedure to handle and recover from asynchronous PCIE link down events on Armada SoCs. The procedure is defined as the following: 1) Prevent new access to the PCI-E I/F by disabling the LTSSM 2) Flush all pending transaction/access to the PCI-E I/F 3) HW reset the PCIE end point device (based on board support) 4) Reset the PCIE MAC 5) Reinitialize the PCIE root complex and enable the LTSSM The execution of this procedure is triggered by the PCIE RST_LINK_DOWN interrupt Ben Peled (5): PCI: armada8k: Disable LTSSM on link down interrupts PCI: armada8k: Add link-down handle PCI: armada8k: add device reset to link-down handle dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings arm64: dts: marvell: add pcie mac reset to pcie Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 + arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 ++ drivers/pci/controller/dwc/pcie-armada8k.c | 126 ++++++++++++++++++++ 3 files changed, 139 insertions(+)
From: Ben Peled <bpeled@marvell.com> The following patches implement the required procedure to handle and recover from asynchronous PCIE link down events on Armada SoCs. The procedure is defined as the following: 1) Prevent new access to the PCI-E I/F by disabling the LTSSM 2) Flush all pending transaction/access to the PCI-E I/F 3) HW reset the PCIE end point device (based on board support) 4) Reset the PCIE MAC 5) Reinitialize the PCIE root complex and enable the LTSSM The execution of this procedure is triggered by the PCIE RST_LINK_DOWN interrupt Ben Peled (5): PCI: armada8k: Disable LTSSM on link down interrupts PCI: armada8k: Add link-down handle PCI: armada8k: add device reset to link-down handle dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings arm64: dts: marvell: add pcie mac reset to pcie Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 + arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 ++ drivers/pci/controller/dwc/pcie-armada8k.c | 126 ++++++++++++++++++++ 3 files changed, 139 insertions(+)