From patchwork Tue Jan 8 16:24:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10752339 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 23378746 for ; Tue, 8 Jan 2019 16:24:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 106C926BE9 for ; Tue, 8 Jan 2019 16:24:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 03DCF27FB7; Tue, 8 Jan 2019 16:24:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D243F27B81 for ; Tue, 8 Jan 2019 16:24:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729172AbfAHQYs (ORCPT ); Tue, 8 Jan 2019 11:24:48 -0500 Received: from mail.bootlin.com ([62.4.15.54]:44823 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728211AbfAHQYs (ORCPT ); Tue, 8 Jan 2019 11:24:48 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 1325D209D7; Tue, 8 Jan 2019 17:24:45 +0100 (CET) Received: from localhost.localdomain (aaubervilliers-681-1-45-241.w90-88.abo.wanadoo.fr [90.88.163.241]) by mail.bootlin.com (Postfix) with ESMTPSA id A4EDE207A3; Tue, 8 Jan 2019 17:24:44 +0100 (CET) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Thomas Petazzoni , Bjorn Helgaas Cc: , Rob Herring , Mark Rutland , Lorenzo Pieralisi , linux-pci@vger.kernel.org, , , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Miquel Raynal Subject: [PATCH v3 00/15] Bring suspend to RAM support to PCIe Aardvark driver Date: Tue, 8 Jan 2019 17:24:25 +0100 Message-Id: <20190108162441.5278-1-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hello, As part of an effort to bring suspend to RAM support to Armada 3700 SoCs (main target: ESPRESSObin), this series handles the work around the PCIe IP. First, more configuration is done in the 'setup' helper as inspired from the U-Boot driver. This is needed to entirely initialize the IP during future resume operation (patch 1). Then, reset GPIO, PHY and clock support are introduced (patch 2-4). As current device trees do not provide the corresponding properties, not finding one of these properties is not an error and just produces a warning. However, if the property is present, an error during PHY initialization will fail the probe of the driver. Note: To be sure the clock will be resumed before this driver, a first series adding links between clocks and consumers has been submitted, see [1]. Anyway, having the clock series applied first is not needed. Patch 5 adds suspend/resume hooks, re-using all the above. Finally, bindings and device trees are updated to reflect the hardware (patch 6-12). While the clock depends on the SoC, the reset GPIO and the PHY depends on the board so the clock is added in the armada-37xx.dtsi file while the two other properties are added in armada-3720-espressobin.dts. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2019-January/623885.html Thanks, Miquèl Changes since v2: ================= * Minor patches reordering. * Added pinctrl patches from Gregory Clement fixing the PCIe pins. His changes implied modifications in the DT/bindings patches adding PCIe reset pin support. * Added a new patch that enlarges the PIO timeout of the driver (explanations in the commit log). * With the timeout changed, removed the "experimental delay" that was needed at resume time before accessing any register. Changes since v1: ================= * Change the capitalization in commit titles to follow the PCI subsystem rules. * Added Suggested-by tag to the patch adding PHY support and to the patch adding the PHY property in the DT. * Added Rob's Reviewed-by tags on bindings. * I am following the discussion about calling functions that might sleep in a NOIRQ context. As there is no real problem yet (as per my understanding), I did not change anything on this regard. Miquel Raynal (15): PCI: aardvark: Enlarge PIO timeout PCI: aardvark: Configure more registers in the configuration helper PCI: aardvark: Add clock support PCI: aardvark: Add PHY support PCI: aardvark: Add PCIe warm reset support PCI: aardvark: Add external reset GPIO support PCI: aardvark: Add suspend to RAM support dt-bindings: PCI: aardvark: Describe the clocks property dt-bindings: PCI: aardvark: Describe the PHY property dt-bindings: PCI: aardvark: Describe the PCIe endpoint card reset pins dt-bindings: PCI: aardvark: Describe the reset-gpios property ARM64: dts: marvell: armada-37xx: declare PCIe clock ARM64: dts: marvell: armada-3720-espressobin: declare PCIe PHY ARM64: dts: marvell: armada-37xx: declare PCIe reset pin ARM64: dts: marvell: armada-3720-espressobin: declare PCIe warm reset pin .../devicetree/bindings/pci/aardvark-pci.txt | 14 ++ .../dts/marvell/armada-3720-espressobin.dts | 3 + arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 + drivers/pci/controller/pci-aardvark.c | 217 +++++++++++++++++- 4 files changed, 243 insertions(+), 1 deletion(-)