From patchwork Fri Feb 15 16:24:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daire McNamara X-Patchwork-Id: 10815407 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A4D1914E1 for ; Fri, 15 Feb 2019 16:24:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91CA62FA7E for ; Fri, 15 Feb 2019 16:24:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 85C692FB68; Fri, 15 Feb 2019 16:24:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 75DE92FB5B for ; Fri, 15 Feb 2019 16:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726388AbfBOQYj (ORCPT ); Fri, 15 Feb 2019 11:24:39 -0500 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:13589 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725939AbfBOQYj (ORCPT ); Fri, 15 Feb 2019 11:24:39 -0500 X-IronPort-AV: E=Sophos;i="5.58,373,1544511600"; d="scan'208";a="26801961" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 15 Feb 2019 09:24:38 -0700 Received: from microchip.com (10.10.76.4) by chn-sv-exch02.mchp-main.com (10.10.76.38) with Microsoft SMTP Server id 14.3.352.0; Fri, 15 Feb 2019 09:24:38 -0700 From: Daire McNamara To: , CC: Daire McNamara Subject: [PATCH v3 0/3] Add Microchip/Microsemi PolarFire SoC PCIe support Date: Fri, 15 Feb 2019 16:24:21 +0000 Message-ID: <20190215162424.564-1-daire.mcnamara@microchip.com> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This v3 patch series adds support for PCIe IP block on Microsemi/Microchip PolarFire SoCs. Updates since v2: o Split out DT bindings and Vendor ID updates into their own patch from PCIe driver. o Updated ChangeLog. Updates since v1: o Incorporate feedback from Bjorn Helgaas. Thanx, Daire Daire McNamara (3): PCI: Add vendor ID for Microsemi dt-bindings: PCI: microsemi: Add DT Bindings for Microsemi PCIe host controller PCI: microsemi: Add host driver for Microsemi PCIe controller .../bindings/pci/microsemi-pcie.txt | 65 ++ .../devicetree/bindings/vendor-prefixes.txt | 1 + drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-microsemi.c | 764 ++++++++++++++++++ 5 files changed, 839 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/microsemi-pcie.txt create mode 100644 drivers/pci/controller/pcie-microsemi.c