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[RFC,0/2] PCI: Add basic Compute eXpress Link DVSEC decode

Message ID 20200515175528.980103-1-sean.v.kelley@linux.intel.com (mailing list archive)
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Series PCI: Add basic Compute eXpress Link DVSEC decode | expand

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Sean V Kelley May 15, 2020, 5:55 p.m. UTC 
This patch series implements basic Designated Vendor-Specific Extended
Capabilities (DVSEC) decode for Compute eXpress Link devices, a new CPU
interconnect building upon PCIe. As a basis for the CXL support it provides
PCI init handling for detection, decode, and caching of CXL device
capabilities.  Moreover, it makes use of the DVSEC Vendor ID and DVSEC ID so
as to identify a CXL capable device. (PCIe r5.0, sec 7.9.6.2)

DocLink: https://www.computeexpresslink.org/

For your reference, a parallel series of patches have been submitted to enable
lspci decode of CXL DVSEC and may be tracked.

Link: https://lore.kernel.org/linux-pci/20200511174618.10589-1-sean.v.kelley@linux.intel.com/

This patch makes use of pending DVSEC related header additions and the
first patch of that series is included here. It can be sorted out when the
upstream merge is done.

Link: https://lore.kernel.org/linux-pci/20200508021844.6911-2-david.e.box@linux.intel.com/

Sample dmesg output of a CXL Type 3 device (CXL.io, CXL.mem):
[    2.997177] pci 0000:6b:00.0: CXL: Cache- IO+ Mem+ Viral- HDMCount 1
[    2.997188] pci 0000:6b:00.0: CXL: cap ctrl status ctrl2 status2 lock
[    2.997201] pci 0000:6b:00.0: CXL: 001e 0002 0000 0000 0000 0000


David E. Box (1):
  pci: Add Designated Vendor Specific Capability

Sean V Kelley (1):
  PCI: Add basic Compute eXpress Link DVSEC decode

 drivers/pci/Kconfig           |  9 ++++
 drivers/pci/Makefile          |  1 +
 drivers/pci/cxl.c             | 89 +++++++++++++++++++++++++++++++++++
 drivers/pci/pci.h             |  7 +++
 drivers/pci/probe.c           |  1 +
 include/linux/pci.h           |  1 +
 include/uapi/linux/pci_regs.h |  5 ++
 7 files changed, 113 insertions(+)
 create mode 100644 drivers/pci/cxl.c

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