From patchwork Thu Sep 10 03:45:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 11766457 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C445392C for ; Thu, 10 Sep 2020 03:47:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A812C21D6C for ; Thu, 10 Sep 2020 03:47:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="dssjgq5b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728363AbgIJDrt (ORCPT ); Wed, 9 Sep 2020 23:47:49 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52089 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727055AbgIJDrp (ORCPT ); Wed, 9 Sep 2020 23:47:45 -0400 X-UUID: e386fe9b4cd04378bb9bcd192e68287d-20200910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=i74HM4n2z7CpO2GU1v53gI/FrljpvWxIeevuuyVHQjk=; b=dssjgq5bRR4rflvQw5PY5rjvXWvN0834CfeY04OpF8BPQCTWMSXBucmgSJWsQlQew+waKuKZdFGbTOlwx5aHJbubNbfhYe2b9166PRNSCyXQ/kvZOISgty2K5cJGsp6EJ38CgR+4XxI4XdIlHmPFINq7hy6v8C3ZsErN42gLPrQ=; X-UUID: e386fe9b4cd04378bb9bcd192e68287d-20200910 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1341551757; Thu, 10 Sep 2020 11:47:43 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Sep 2020 11:47:40 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Sep 2020 11:47:40 +0800 From: Jianjun Wang To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee CC: Philipp Zabel , Matthias Brugger , Mauro Carvalho Chehab , , , , , , , Sj Huang , Jianjun Wang Subject: [v2,0/3] PCI: mediatek: Add new generation controller support Date: Thu, 10 Sep 2020 11:45:33 +0800 Message-ID: <20200910034536.30860-1-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org These series patches add pcie-mediatek-gen3.c and dt-bindings file to support new generation PCIe controller. Change in v2: 1. Fix the typo of dt-bindings patch 2. Remove the unnecessary properties in binding document 3. dispos the irq mappings of msi top domain when irq teardown Jianjun Wang (3): dt-bindings: PCI: mediatek: Add YAML schema PCI: mediatek: Add new generation controller support MAINTAINERS: update entry for MediaTek PCIe controller .../bindings/pci/mediatek-pcie-gen3.yaml | 130 ++ MAINTAINERS | 1 + drivers/pci/controller/Kconfig | 14 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++++++++++++++++ 5 files changed, 1222 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c