From patchwork Sun Sep 27 07:45:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 11801923 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6485C112C for ; Sun, 27 Sep 2020 07:48:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38D272399A for ; Sun, 27 Sep 2020 07:48:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="o4qFlUBL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727263AbgI0Hsg (ORCPT ); Sun, 27 Sep 2020 03:48:36 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:57794 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726382AbgI0Hsf (ORCPT ); Sun, 27 Sep 2020 03:48:35 -0400 X-UUID: 41f7c2f5dcb64a769089f932eb3d2dcc-20200927 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=d9lyIqtPvPXiR0F6KUQePPMfpcjXX/jEbkNNHhsMUyo=; b=o4qFlUBL8p6PM/BoSI4Fh75nQ9SKQjn9e07CFDjyzLqE+i40/+JT5ZppBXM9OcnX9nEwgZ0e+/U8ZW+ygxl6GtjXfj80Lz7wXaEDrN9YLZsDFU9+QZltD2MWM6U/CTIL1bE0jud3Iwp5W6ixq2Gf+ZCUjxRLYxZgzetCcMWxQu4=; X-UUID: 41f7c2f5dcb64a769089f932eb3d2dcc-20200927 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 219952987; Sun, 27 Sep 2020 15:48:29 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 27 Sep 2020 15:48:26 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 27 Sep 2020 15:48:25 +0800 From: Jianjun Wang To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee CC: Philipp Zabel , Matthias Brugger , Mauro Carvalho Chehab , , , , , , , Sj Huang , Jianjun Wang , , , , Subject: [v3,0/3] PCI: mediatek: Add new generation controller support Date: Sun, 27 Sep 2020 15:45:52 +0800 Message-ID: <20200927074555.4155-1-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: FEC9D6A66C7B483EF0EF7CCF5000DE10A76B54A9207FFC0B54437214FC778F142000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org These series patches add pcie-mediatek-gen3.c and dt-bindings file to support new generation PCIe controller. Changes in v3: 1. Remove standard property in binding document 2. Return error number when get_optional* API throws an error 3. Use the bulk clk APIs Changes in v2: 1. Fix the typo of dt-bindings patch 2. Remove the unnecessary properties in binding document 3. dispos the irq mappings of msi top domain when irq teardown Jianjun Wang (3): dt-bindings: PCI: mediatek: Add YAML schema PCI: mediatek: Add new generation controller support MAINTAINERS: update entry for MediaTek PCIe controller .../bindings/pci/mediatek-pcie-gen3.yaml | 126 ++ MAINTAINERS | 1 + drivers/pci/controller/Kconfig | 14 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-mediatek-gen3.c | 1024 +++++++++++++++++ 5 files changed, 1166 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c