From patchwork Tue Aug 3 07:49:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 12415489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74790C432BE for ; Tue, 3 Aug 2021 07:49:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B5B860F70 for ; Tue, 3 Aug 2021 07:49:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234148AbhHCHuF (ORCPT ); Tue, 3 Aug 2021 03:50:05 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35722 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234271AbhHCHuF (ORCPT ); Tue, 3 Aug 2021 03:50:05 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1737ndL5031663; Tue, 3 Aug 2021 02:49:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1627976979; bh=jU6NdUOo1QvDJP+eJFQCU2O42F89bmLL3ZejTmPvGHk=; h=From:To:CC:Subject:Date; b=dSQa9pc7mip0liDz7RQSJn4WMD2X1/FGOvkztAz/4xNW5Yapv+Bgj8HDjknIyCbio D1aaKTyNHYIOR9JLS2jKg+d/9Rm1eTcJhUkHl176RDLMX+nOLlPczPBiprr0kLC9Je kH26BZGGTyy5p8ZTvqOF1a2l+SBDdEOCTOh/w/nc= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1737ndu4120998 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 3 Aug 2021 02:49:39 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 3 Aug 2021 02:49:38 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 3 Aug 2021 02:49:38 -0500 Received: from a0393678-ssd.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1737nXrv045202; Tue, 3 Aug 2021 02:49:34 -0500 From: Kishon Vijay Abraham I To: Lorenzo Pieralisi , Arnd Bergmann , Rob Herring , Bjorn Helgaas CC: Lokesh Vutla , , Greg Kroah-Hartman , Tom Joseph , , , , , Subject: [PATCH v2 0/6] PCI: Add support for J7200 and AM64 Date: Tue, 3 Aug 2021 13:19:26 +0530 Message-ID: <20210803074932.19820-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This series adds the compatible specific to J7200 and AM64 and applies the erratas and configuration specific to them. This series also includes Nadeem's patch that adds a quirk in Cadence driver which is used by J7200 [1]. The DT binding for both J7200 and AM64 is already merged. v1 of the patch series can be found at [2] Changes from v1: 1) As suggested by Bjorn, used unsigned int :1, instead of bool for structure members 2) Removed using unnecessary local variables and also fixed some code alignment [1] -> https://lore.kernel.org/r/20210528155626.21793-1-nadeem@cadence.com [2] -> https://lore.kernel.org/r/20210706105035.9915-1-kishon@ti.com Kishon Vijay Abraham I (5): PCI: cadence: Use bitfield for *quirk_retrain_flag* instead of bool PCI: j721e: Add PCIe support for J7200 PCI: j721e: Add PCIe support for AM64 misc: pci_endpoint_test: Do not request or allocate IRQs in probe misc: pci_endpoint_test: Add deviceID for AM64 and J7200 Nadeem Athani (1): PCI: cadence: Add quirk flag to set minimum delay in LTSSM Detect.Quiet state drivers/misc/pci_endpoint_test.c | 27 ++++++-- drivers/pci/controller/cadence/pci-j721e.c | 61 +++++++++++++++++-- .../pci/controller/cadence/pcie-cadence-ep.c | 4 ++ .../controller/cadence/pcie-cadence-host.c | 3 + drivers/pci/controller/cadence/pcie-cadence.c | 17 ++++++ drivers/pci/controller/cadence/pcie-cadence.h | 17 +++++- 6 files changed, 117 insertions(+), 12 deletions(-)