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Sat, 5 Feb 2022 08:21:47 -0800 From: Vidya Sagar To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH V1 00/10] PCI: tegra: Add Tegra234 PCIe support Date: Sat, 5 Feb 2022 21:51:34 +0530 Message-ID: <20220205162144.30240-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c3fd54b6-fb04-4053-e224-08d9e8c39f61 X-MS-TrafficTypeDiagnostic: BL0PR12MB2564:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XnaYQg8qwGO6CCs2xlh9LaXgXzIxN++TZGKydhmLfsuAVR7kXm/yDuSvFJag9pnwf8mdvnddXcLmbrGuBnGo+nwR+9ezQmZFu81CWW3gqR98j4zNfJAaOhMc4c4xdgMEZZ3dl3+ZKsnvcClUY9y+06YzPZtIwiVk9ck8SaATN+7YDY+RfpJXgs3k9cjwmvX1mrTSflKGX4LE+fC9j/S8c0iAneop2EMUi7l+7/10Fu0KrKmx0/o1c+0GxYin51ZPRwlSePJwAppcxaiv31W7M/c7wUJswgl25XmOBmDE/5iddG/+eqadsAkGe7RVI4k+lcAL1Odl7jRwzjGbm9SL1ybHU9M7U0aRRFw1g20/3hkMlVT6PPq00qKuNNH801wdJGUVAlXh0pTaZBS8fPli1sMnldCSM/5Zwi0PjqSQF4G7bLcZuvBqOLDCuAaPzKCNhESgjD9mq9nMEDxq+IPQHT43YNgQxYZc4ENSgwE+pRi3qkvepr3bQheEy6+WbcBtDO94M5GCHP08TfDL+ugFMMHrRw8uUXSgM7uYv6cUYkyI1hdzEllqtNwgqcSt+J64XiabLjX0RYdXx9bASnRXH5BFjZabhHATONY2FiJh7tqV1X0TK23cJTCVdyOdEkIdMfVGHNKMnJQym6tIMRHARhrP3RdOFeWkaPIJSyvfwsbintAeYITl7S0bhExGJW4jaCiPtg6MElERSTJExPHKqw== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(7696005)(110136005)(6666004)(86362001)(26005)(1076003)(6636002)(316002)(356005)(81166007)(54906003)(2616005)(186003)(426003)(8676002)(4326008)(508600001)(8936002)(336012)(7416002)(70586007)(82310400004)(70206006)(47076005)(2906002)(40460700003)(83380400001)(5660300002)(36860700001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2022 16:21:53.8801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3fd54b6-fb04-4053-e224-08d9e8c39f61 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2564 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra234 has a total of 11 PCIe controllers based on Synopsys DesignWare core. There are three Universal PHY (UPHY) blocks (viz. HSIO, NVHS and GBE) with each block supporting 8 lanes respectively. Controllers:0~4 use UPHY lanes from HSIO block, Controllers:5,6 use UPHY lanes from NVHS block and Controllers:7~10 use UPHY lanes from GBE block. Lane mapping in each block is controlled in XBAR module by BPMP-FW. Since PCIe core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used to connect each UPHY lane (applicable to all three UPHY bricks i.e. HSIO/NVHS/GBE) to PCIe controller. This patch series - Adds support for Tegra234 in the existing P2U PHY driver - Adds support for Tegra234 in the existing PCIe platform controller driver - Adds device tree nodes each PCIe controllers - Enables nodes applicable to P3737-0000 platform Testing done on P3737-0000 platform - PCIe link is up with on-board Broadcom WiFi controller - PCIe link is up with NVMe drive connected to M.2 Key-M slot and its functionality is verified - PCIe link is up with a variety of cards (NICs and USB3.0 add-on cards) and their functionality is verified Vidya Sagar (10): dt-bindings: Add Tegra234 PCIe clocks and resets dt-bindings: power: Add Tegra234 PCIe power domains dt-bindings: memory: Add Tegra234 PCIe memory dt-bindings: PHY: P2U: Add support for Tegra234 P2U block dt-bindings: PCI: tegra: Add device tree support for Tegra234 arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT arm64: tegra: Enable PCIe slots in P3737-0000 board phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 PCI: Disable MSI for Tegra234 root ports PCI: tegra: Add Tegra234 PCIe support .../bindings/pci/nvidia,tegra194-pcie.txt | 106 ++- .../bindings/phy/phy-tegra194-p2u.yaml | 17 +- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 26 + arch/arm64/boot/dts/nvidia/tegra234.dtsi | 743 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 409 +++++++--- drivers/pci/quirks.c | 9 + drivers/phy/tegra/phy-tegra194-p2u.c | 48 +- include/dt-bindings/clock/tegra234-clock.h | 25 +- include/dt-bindings/memory/tegra234-mc.h | 64 ++ .../dt-bindings/power/tegra234-powergate.h | 20 + include/dt-bindings/reset/tegra234-reset.h | 27 +- 11 files changed, 1390 insertions(+), 104 deletions(-) create mode 100644 include/dt-bindings/power/tegra234-powergate.h