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Tue, 5 Jul 2022 03:56:50 -0700 Envelope-to: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, bhelgaas@google.com Received: from [10.140.9.2] (port=51530 helo=xhdbharatku40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o8gEb-000FEX-Th; Tue, 05 Jul 2022 03:56:50 -0700 From: Bharat Kumar Gogada To: , CC: , , Bharat Kumar Gogada Subject: [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port Date: Tue, 5 Jul 2022 16:26:44 +0530 Message-ID: <20220705105646.16980-1-bharat.kumar.gogada@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea750c98-d473-4b7d-0b02-08da5e7510bb X-MS-TrafficTypeDiagnostic: DM6PR02MB5771:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5p0aO1uw3VcBJ7p/fvG8x5lea7jSR+RCQQXza9Q46qnXByICcOke1dMyZU8Zs7p3+KOFNHGqn+B0/8qHjmo1edx29X6ITdoqsFCvRLkY9ozVAhmqKTD6sscc9C7Od9h0UrXRLgAYVbW4zBa+eDGZsTH4oSgRIWp7sq+LEvgjDMrPGA8hI3nAmPGVgUDJ00bPEkJuPX7f6ETJBXS6Lwnf2COSDscrocPtqCe5L/DgG6f0cZueg50mRuWW6OcBb0/va2OZCpbGy7XlA5kC7RcAAwTQrL556A2qu3JwV1hMwJ+fkCtg8z0VrPg5MqiAbz2d/xpe/m0A9IDQebQQ7QY9On+bVyQKNYkT0LTFhsAXjkaHmsn+tM7jMNwIRazzO+QyETcr95X0u+3iSxTH0b9IgjOnFQnyjVApjn+1nUSe/yTfHcn2Drn9yAEuwmmovVuo0sksm+WIUZVhaqTIh0zm+0YUQ1eIMFCbbRu20dqeg0eG9VjkkAM9IsFld1xipiOXfemEiUZk7T4iaatxznnLBCK8i0TgxA7TKy2aLBiFyd0mn9BFYnm5jfvHcEJTEl27YL6db8ic/UgRkGuolRMSyZYHghDLhoxlT/DGNMvS4rbG8VUPuzmVEmrOcr5fLRkHNkNEt8jt29hFJjzF3FuPxcy1iWYkfR4TduUp6JsI1pGfbP85/B3J5E9Oh+B7i6G3fQTCNHaciH1w9Jb5X+UFLUGnCpzE/ySPzPIY5Ag7BC3KMEtGlwwVLVBUhZL3iWq+L17iL3HLwKzjAHEaHGqvCe4AAvH1tUuoKvbK7tupzhGvqroo8EocwG/FhZJriU7byYwcwT1JrWjOHSKOfmNCNyZVpL6VpbI3nM9syiEqzp0= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230016)(4636009)(396003)(376002)(39860400002)(346002)(136003)(46966006)(40470700004)(36840700001)(36860700001)(40480700001)(7696005)(8936002)(478600001)(5660300002)(7636003)(2906002)(70586007)(41300700001)(103116003)(356005)(82740400003)(70206006)(4744005)(6666004)(8676002)(4326008)(82310400005)(36756003)(186003)(47076005)(110136005)(426003)(336012)(26005)(54906003)(40460700003)(107886003)(1076003)(2616005)(9786002)(83380400001)(316002)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2022 10:56:51.0287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea750c98-d473-4b7d-0b02-08da5e7510bb X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT019.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5771 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additional register bit to enable and handle legacy interrupts. Changes in v6: - Added of_device_get_match_data to identify CPM version. - Used enum values to differentiate CPM version. Bharat Kumar Gogada (2): dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port PCI: xilinx-cpm: Add support for Versal CPM5 Root Port .../bindings/pci/xilinx-versal-cpm.yaml | 38 ++++++++++- drivers/pci/controller/pcie-xilinx-cpm.c | 64 ++++++++++++++++++- 2 files changed, 98 insertions(+), 4 deletions(-)