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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2022 14:21:13.4651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f3d5a86-1b95-478a-5970-08da6b244452 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0272 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra234 has a total of 11 PCIe controllers based on Synopsys DesignWare core. There are three Universal PHY (UPHY) blocks (viz. HSIO, NVHS and GBE) with each block supporting 8 lanes respectively. Controllers:0~4 use UPHY lanes from HSIO block, Controllers:5,6 use UPHY lanes from NVHS block and Controllers:7~10 use UPHY lanes from GBE block. Lane mapping in each block is controlled in XBAR module by BPMP-FW. Since PCIe core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used to connect each UPHY lane (applicable to all three UPHY bricks i.e. HSIO/NVHS/GBE) to PCIe controller. All the controllers can operate in the RootPort mode where as only controllers C5, C6, C7 and C10 can operate in the EndPoint mode. This patch series - Adds support for Tegra234 in the existing P2U PHY driver - Adds support for Tegra234 in the existing PCIe platform controller driver - Adds device tree nodes for all PCIe controllers - Enables nodes applicable to P3737-0000 platform Testing done on P3737-0000 platform - PCIe link is up with on-board Broadcom WiFi controller - PCIe link is up with an NVMe drive connected to M.2 Key-M slot and its functionality is verified - PCIe link is up with a variety of cards (NICs and USB3.0 add-on cards) connected to CEM slot and their functionality is verified - PCIe link is up with C5 controller configured for the endpoint mode with a host V6: * Addressed review comments from Bjorn * Moved out non-Tegra234 specific changes and created separate patches V5: * Addressed review comments from Rob V4: * Addressed review comments from Krzysztof and Rob * Changes are only in schema files and regulator patch * Dropped PHY related patches as they are already accepted V3: * Add DT nodes for the controllers that can work in the EndPoint mode * Converted the existing device-tree binding documentation from .txt to .yaml * Add T234 specific information to the RP and EP .yaml documentation files * Added regulators required to power up required power rails V2: * Dropped 3 patches that add clocks & resets IDs, power-domain IDs and memory IDs for PCIe controllers as the patches are already available in linux-next * Based on Bjorn's review comment, reverted the commit b57256918399 ("PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie") and pushed it as a separate patch before adding support for T234 in the existing driver * Addressed review comments from Rob for the other changes Vidya Sagar (16): dt-bindings: pci: tegra: Convert to json-schema dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode arm64: tegra: Add regulators required for PCIe arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT arm64: tegra: Enable PCIe slots in P3737-0000 board PCI: Disable MSI for Tegra234 root ports Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" PCI: tegra194: Find RAS DES PCIe capability offset PCI: tegra194: Fix root port interrupt handling PCI: tegra194: Clear bandwidth management status PCI: tegra194: Enable support for 256 Byte payload PCI: tegra194: Cleanup the exit path for endpoint mode PCI: tegra194: Fix link up retry sequence PCI: tegra194: Extend endpoint mode support PCI: tegra: Add Tegra234 PCIe support .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 318 ++++++ .../bindings/pci/nvidia,tegra194-pcie.txt | 245 ----- .../bindings/pci/nvidia,tegra194-pcie.yaml | 349 +++++++ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 4 +- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 36 + .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 51 + arch/arm64/boot/dts/nvidia/tegra234.dtsi | 927 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 19 + drivers/pci/controller/dwc/pcie-tegra194.c | 658 ++++++++----- drivers/pci/quirks.c | 13 +- 10 files changed, 2136 insertions(+), 484 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml