mbox series

[V4,0/2] PCI/ASPM: Save/restore L1SS Capability for suspend/resume

Message ID 20220913131822.16557-1-vidyas@nvidia.com (mailing list archive)
Headers show
Series PCI/ASPM: Save/restore L1SS Capability for suspend/resume | expand

Message

Vidya Sagar Sept. 13, 2022, 1:18 p.m. UTC 
This patch series saves and restores the ASPM L1SS capability registers
during suspend/resume cycle of the system.
First patch refactors the existing L1SS register programming code to
take out the common code.
Second patch adds support to save and restore of the L1SS registers using
the common code extracted in the first patch to restore the registers.

This patch is verified on Tegra194 and Tegra234 platforms.

Vidya Sagar (2):
  PCI/ASPM: Refactor ASPM L1SS control register programming
  PCI/ASPM: Save/restore L1SS Capability for suspend/resume

 drivers/pci/pci.c       |   7 +++
 drivers/pci/pci.h       |   4 ++
 drivers/pci/pcie/aspm.c | 106 +++++++++++++++++++++++++++-------------
 3 files changed, 83 insertions(+), 34 deletions(-)

Comments

Bjorn Helgaas Sept. 13, 2022, 5:17 p.m. UTC | #1 
On Tue, Sep 13, 2022 at 06:48:20PM +0530, Vidya Sagar wrote:
> This patch series saves and restores the ASPM L1SS capability registers
> during suspend/resume cycle of the system.
> First patch refactors the existing L1SS register programming code to
> take out the common code.
> Second patch adds support to save and restore of the L1SS registers using
> the common code extracted in the first patch to restore the registers.
> 
> This patch is verified on Tegra194 and Tegra234 platforms.
> 
> Vidya Sagar (2):
>   PCI/ASPM: Refactor ASPM L1SS control register programming
>   PCI/ASPM: Save/restore L1SS Capability for suspend/resume
> 
>  drivers/pci/pci.c       |   7 +++
>  drivers/pci/pci.h       |   4 ++
>  drivers/pci/pcie/aspm.c | 106 +++++++++++++++++++++++++++-------------
>  3 files changed, 83 insertions(+), 34 deletions(-)

Applied to pci/aspm for v6.1, thanks!

I dropped the pci_is_pcie() testing since pci_configure_ltr() only
sets dev->l1ss for PCIe devices.