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Thu, 24 Nov 2022 00:35:23 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 24 Nov 2022 00:35:22 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Thu, 24 Nov 2022 00:35:18 -0800 From: Manikanta Maddireddy To: , , , , , CC: , , , , , , , , Manikanta Maddireddy Subject: [IP REVIEW PATCH 0/3] Add support for Lane Margining at Receiver Date: Thu, 24 Nov 2022 14:05:07 +0530 Message-ID: <20221124083510.3008139-1-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT061:EE_|CH2PR12MB4230:EE_ X-MS-Office365-Filtering-Correlation-Id: 14bdc38a-e70c-49d0-0139-08dacdf6dbda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2022 08:35:35.9086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14bdc38a-e70c-49d0-0139-08dacdf6dbda X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4230 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra234 supports Lane Margining at Receiver feature. However, this requires programming of per lane PIPE2UPHY hardware instance to relay the lane margin control and margin status information between PCIe controller and UPHY modules. This series adds this support in PIPE2UPHY driver. Manikanta Maddireddy (3): phy: tegra: p2u: Add lane margin support dts: soc: t234: Add uphy lane number and intr in p2u nodes dt-bindings: PHY: P2U: Add PCIe lane margining support .../bindings/phy/phy-tegra194-p2u.yaml | 50 ++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 120 ++++++++ drivers/phy/tegra/phy-tegra194-p2u.c | 274 ++++++++++++++++++ 3 files changed, 444 insertions(+)