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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000014.mail.protection.outlook.com (10.167.244.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7587.0 via Frontend Transport; Thu, 9 May 2024 16:27:48 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 9 May 2024 11:27:47 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , Subject: [PATCH V1 0/9] PCIe TPH and cache direct injection support Date: Thu, 9 May 2024 11:27:32 -0500 Message-ID: <20240509162741.1937586-1-wei.huang2@amd.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000014:EE_|IA1PR12MB7663:EE_ X-MS-Office365-Filtering-Correlation-Id: bc2761ae-b4f5-43a9-41db-08dc7044f6e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|7416005|82310400017|36860700004|1800799015; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2024 16:27:48.1646 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc2761ae-b4f5-43a9-41db-08dc7044f6e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000014.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7663 Hi All, TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices to provide optimization hints for requests that target memory space. These hints, in a format called steering tag (ST), are provided in the requester's TLP headers and allow the system hardware, including the Root Complex, to optimize the utilization of platform resources for the requests. Upcoming AMD hardware implement a new Cache Injection feature that leverages TPH. Cache Injection allows PCIe endpoints to inject I/O Coherent DMA writes directly into an L2 within the CCX (core complex) closest to the CPU core that will consume it. The technology is targeted at applications whose performance is sensitive to the latency of inbound writes as seen by a CPU core. The applications include networking and storage applications. This series implements generic TPH support in Linux. It allows STs to be retrieved from ACPI _DSM (defined by ACPI) and used by PCIe end-point drivers as needed. As a demo, it includes an usage example in Broadcom BNXT driver. When running on Broadcom NICs with proper firmware, Cache Injection shows substantial memory bandwidth saving using real-world benchmarks. Manoj Panicker (1): bnxt_en: Add TPH support in BNXT driver Michael Chan (1): bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Wei Huang (7): PCI: Introduce PCIe TPH support framework PCI: Add TPH related register definition PCI/TPH: Implement a command line option to disable TPH PCI/TPH: Implement a command line option to force No ST Mode PCI/TPH: Introduce API functions to get/set steering tags PCI/TPH: Retrieve steering tag from ACPI _DSM PCI/TPH: Add TPH documentation Documentation/PCI/index.rst | 1 + Documentation/PCI/tph.rst | 57 ++ .../admin-guide/kernel-parameters.txt | 2 + Documentation/driver-api/pci/pci.rst | 3 + drivers/net/ethernet/broadcom/bnxt/bnxt.c | 59 +- drivers/net/ethernet/broadcom/bnxt/bnxt.h | 4 + drivers/pci/pci-driver.c | 12 +- drivers/pci/pci.c | 24 + drivers/pci/pci.h | 6 + drivers/pci/pcie/Kconfig | 10 + drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/tph.c | 563 ++++++++++++++++++ drivers/pci/probe.c | 1 + drivers/vfio/pci/vfio_pci_config.c | 7 +- include/linux/pci-tph.h | 75 +++ include/linux/pci.h | 6 + include/uapi/linux/pci_regs.h | 35 +- 17 files changed, 856 insertions(+), 10 deletions(-) create mode 100644 Documentation/PCI/tph.rst create mode 100644 drivers/pci/pcie/tph.c create mode 100644 include/linux/pci-tph.h