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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D5.mail.protection.outlook.com (10.167.241.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Thu, 13 Jun 2024 05:42:42 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 13 Jun 2024 00:42:40 -0500 From: Mario Limonciello To: Bjorn Helgaas , Mathias Nyman , Greg Kroah-Hartman CC: "open list:PCI SUBSYSTEM" , open list , "open list:USB XHCI DRIVER" , Daniel Drake , Gary Li , Mika Westerberg , "Mario Limonciello" Subject: [PATCH 0/4] Verify devices transition from D3cold to D0 Date: Thu, 13 Jun 2024 00:42:00 -0500 Message-ID: <20240613054204.5850-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|DM4PR12MB5865:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a94e754-7b84-4878-dd98-08dc8b6ba519 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230034|376008|1800799018|82310400020|36860700007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2024 05:42:42.4340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a94e754-7b84-4878-dd98-08dc8b6ba519 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5865 Gary has reported that when a dock is plugged into a system at the same time the autosuspend delay has tripped that the USB4 stack malfunctions. Messages show up like this: ``` thunderbolt 0000:e5:00.6: ring_interrupt_active: interrupt for TX ring 0 is already enabled ``` Furthermore the USB4 router is non-functional at this point. Those messages happen because the device is still in D3cold at the time that the PCI core handed control back to the USB4 connection manager (thunderbolt). The issue is that it takes time for a device to enter D3cold and do a conventional reset, and then more time for it to exit D3cold. This appears not to be a new problem; previously there were very similar reports from Ryzen XHCI controllers. Quirks were added for those. Furthermore; adding extra logging it's apparent that other PCI devices in the system can take more than 10ms to recover from D3cold as well. This series add a wait into pci_power_up() specifically for D3cold exit and then drops the quirks that were previously used for the Ryzen XHCI controllers. Mario Limonciello (4): PCI: Check PCI_PM_CTRL instead of PCI_COMMAND in pci_dev_wait() PCI: Verify functions currently in D3cold have entered D0 PCI: Allow Ryzen XHCI controllers into D3cold and drop delays PCI: Drop Radeon quirk for Macbook Pro 8.2 drivers/pci/pci.c | 21 ++++++++++++++++----- drivers/pci/quirks.c | 25 ------------------------- drivers/usb/host/xhci-pci.c | 11 ----------- 3 files changed, 16 insertions(+), 41 deletions(-)