mbox series

[0/2] Add support for Xilinx XDMA Soft IP as Root Port

Message ID 20240624110755.133625-1-thippesw@amd.com (mailing list archive)
Headers show
Series Add support for Xilinx XDMA Soft IP as Root Port | expand

Message

Thippeswamy Havalige June 24, 2024, 11:07 a.m. UTC 
This series of patch add support for Xilinx QDMA Soft IP as Root Port.

The Xilinx QDMA Soft IP support's 32 bit and 64bit BAR's.
As Root Port it supports MSI and legacy interrupts.

Thippeswamy Havalige (2):
  dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root
    Port Bridge
  PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver

 .../devicetree/bindings/pci/xlnx,xdma-host.yaml    | 41 +++++++++++++++-
 drivers/pci/controller/pcie-xilinx-dma-pl.c        | 56 ++++++++++++++++++++--
 2 files changed, 92 insertions(+), 5 deletions(-)

Comments

Havalige, Thippeswamy June 24, 2024, 11:11 a.m. UTC | #1 
Ignore this patch series

> -----Original Message-----
> From: Thippeswamy Havalige <thippesw@amd.com>
> Sent: Monday, June 24, 2024 4:38 PM
> To: bhelgaas@google.com; kw@linux.com; robh@kernel.org;
> krzk+dt@kernel.org; conor+dt@kernel.org; lpieralisi@kernel.org
> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Gogada, Bharat Kumar
> <bharat.kumar.gogada@amd.com>; Havalige, Thippeswamy
> <thippeswamy.havalige@amd.com>
> Subject: [PATCH 0/2] Add support for Xilinx XDMA Soft IP as Root Port
> 
> This series of patch add support for Xilinx QDMA Soft IP as Root Port.
> 
> The Xilinx QDMA Soft IP support's 32 bit and 64bit BAR's.
> As Root Port it supports MSI and legacy interrupts.
> 
> Thippeswamy Havalige (2):
>   dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root
>     Port Bridge
>   PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver
> 
>  .../devicetree/bindings/pci/xlnx,xdma-host.yaml    | 41 +++++++++++++++-
>  drivers/pci/controller/pcie-xilinx-dma-pl.c        | 56 ++++++++++++++++++++-
> -
>  2 files changed, 92 insertions(+), 5 deletions(-)
> 
> --
> 1.8.3.1