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Wed, 26 Jun 2024 12:37:56 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:37:51 -0700 From: Krishna chaitanya chundru Subject: [PATCH RFC 0/7] PCI: enable Power and configure the QPS615 PCIe switch Date: Wed, 26 Jun 2024 18:07:48 +0530 Message-ID: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAJwLfGYC/12MsQ7CIBRFf6V5sxhAisapiYkf4Go6kAe1bxBaU KJp+HcJo+O59+RskFwkl+DcbRBdpkTBVxC7DnA2/uEY2coguVRcS8XWJWnRs8kYjqi5xaOCKi/ RTfRpoTvcrhcY6zhTeoX4bfEs2vXfyYJxpk4oDtr0zlgc1jchedxjeMJYSvkBNO8cEKMAAAA= To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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One of the downstream ports is used as endpoint device of Ethernet MAC. Other two downstream ports are supposed to connect to external device. One Host can connect to QPS615 by upstream port. QPS615 switch power is controlled by the GPIO's. After powering on the switch will immediately participate in the link training. if the host is also ready by that time PCIe link will established. The QPS615 needs to configured certain parameters like de-emphasis, disable unused port etc before link is established. These settings vary from platform to platform. As the controller starts link training before the probe of pwrctl driver, the PCIe link may come up before configuring the switch itself. To avoid this introduce two functions in pci_ops to start_link() & stop_link() which will disable the link training if the PCIe link is not up yet. Now PCI pwrctl device is the child of the pci-pcie bridge, if we want to enable the suspend resume for pwrctl device there may be issues since pci bridge will try to access some registers in the config which may cause timeouts or Un clocked access as the power can be removed in the suspend of pwrctl driver. To solve this make PCIe controller as parent to the pci pwr ctrl driver and create devlink between host bridge and pci pwrctl driver so that pci pwrctl driver will go suspend only after all the PCIe devices went to suspend. In pci pwrctl driver use stop_link() to keep the link in D3cold and start_link() to bring back link to D0. This series is developed on top the series: https://lore.kernel.org/lkml/20240612082019.19161-1-brgl@bgdev.pl/ we are sending this series to get coments on the usage of stop_link and start_link which is being add in this series. Signed-off-by: Krishna chaitanya chundru --- Krishna chaitanya chundru (7): dt: bindings: add qcom,qps615.yaml arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node pci: Change the parent of the platform devices for child OF nodes pci: Add new start_link() & stop_link function ops pci: dwc: Add support for new pci function op pci: qcom: Add support for start_link() & stop_link() pci: pwrctl: Add power control driver for qps615 .../devicetree/bindings/pci/qcom,qps615.yaml | 73 ++++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 55 ++++ drivers/pci/bus.c | 5 +- drivers/pci/controller/dwc/pcie-designware-host.c | 19 ++ drivers/pci/controller/dwc/pcie-qcom.c | 108 +++++++- drivers/pci/pwrctl/Kconfig | 7 + drivers/pci/pwrctl/Makefile | 1 + drivers/pci/pwrctl/core.c | 7 +- drivers/pci/pwrctl/pci-pwrctl-qps615.c | 278 +++++++++++++++++++++ include/linux/pci.h | 2 + 10 files changed, 541 insertions(+), 14 deletions(-) --- base-commit: d737627471e5b3962eedae870aa0475d6c9bba18 change-id: 20240624-qps615-faa0cc60dc74 Best regards,