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Sat, 16 Nov 2024 01:37:45 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 17:37:38 -0800 From: Krishna chaitanya chundru Subject: [PATCH 0/4] PCI: dwc: Add support for configuring lane equalization presets Date: Sat, 16 Nov 2024 07:07:29 +0530 Message-ID: <20241116-presets-v1-0-878a837a4fee@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAFn3N2cC/2XMQQ7CIBCF4asY1mJmgJbqynsYF0DBsrBVqETT9 O7Smtgal28y3z+QaIO3kRw2Awk2+ei7Ng/cbohpVHux1Nd5EwZMIHCgt2Cj7SO1BlFxK4TSnOT vfHf+OZdO57wbH/suvOZwwun6aSDgt5GQIi0qzQFrxYHB8f7wxrdmZ7ormSqJrSSyRTIKFF1ZS K1cKSvzL/laikXyLJ0weylBO6PZrxzH8Q0PH1UVFAEAAA== To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= CC: , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, read the device tree property and stores in the presets structure. Based upon the lane width and supported data rate update lane equalization registers. This patch depends on the this dt binding pull request: https://github.com/devicetree-org/dt-schema/pull/146 Signed-off-by: Krishna chaitanya chundru --- Krishna chaitanya chundru (4): arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties PCI: of: Add API to retrieve equalization presets from device tree PCI: dwc: Improve handling of PCIe lane configuration PCI: dwc: Add support for configuring lane equalization presets arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 +++ drivers/pci/controller/dwc/pcie-designware-host.c | 42 +++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 14 ++++- drivers/pci/controller/dwc/pcie-designware.h | 4 ++ drivers/pci/of.c | 62 +++++++++++++++++++++++ drivers/pci/pci.h | 17 ++++++- include/uapi/linux/pci_regs.h | 3 ++ 7 files changed, 147 insertions(+), 3 deletions(-) --- base-commit: 81983758430957d9a5cb3333fe324fd70cf63e7e change-id: 20241030-presets-ec11a3e44ab3 Best regards,