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a=ed25519-sha256; t=1734936683; l=2651; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=lBJfTfyy82CFWAqoyStq/YFskmSdscx2DftkuxI1ipM=; b=Mm0+o0Kq6oZ3EnHMUbhhhR82hhpsA4bkTYPodrKs2rSh51Nd3e+3IjBwjhNEoVt/lyTcpUiih KH5xAWOHyWAC4bm4WycNHQ+ECcbDvuGRW35wAAAiI1asAEFB4AxKaQj X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: anp73qseOOTwTPCR3PL3a2A6NhnkPmIc X-Proofpoint-GUID: anp73qseOOTwTPCR3PL3a2A6NhnkPmIc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 mlxlogscore=948 priorityscore=1501 malwarescore=0 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412230059 PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, read the device tree property and stores in the presets structure. Based upon the lane width and supported data rate update lane equalization registers. This patch depends on the this dt binding pull request which got recently merged: https://github.com/devicetree-org/dt-schema/pull/146 Signed-off-by: Krishna Chaitanya Chundru --- Changes in v3: - In previous series a wrong patch was attached, correct it - Link to v2: https://lore.kernel.org/r/20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com Changes in v2: - Fix the kernel test robot error - As suggested by konrad use for loop and read "eq-presets-%ugts", (8 << i) - Link to v1: https://lore.kernel.org/r/20241116-presets-v1-0-878a837a4fee@quicinc.com --- Krishna Chaitanya Chundru (4): arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties PCI: of: Add API to retrieve equalization presets from device tree PCI: dwc: Improve handling of PCIe lane configuration PCI: dwc: Add support for configuring lane equalization presets arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++ drivers/pci/controller/dwc/pcie-designware-host.c | 42 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++- drivers/pci/controller/dwc/pcie-designware.h | 4 ++ drivers/pci/of.c | 45 +++++++++++++++++++++++ drivers/pci/pci.h | 17 ++++++++- include/uapi/linux/pci_regs.h | 3 ++ 7 files changed, 130 insertions(+), 3 deletions(-) --- base-commit: 87d6aab2389e5ce0197d8257d5f8ee965a67c4cd change-id: 20241212-preset_v2-549b7acda9b7 Best regards,