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Mon, 24 Feb 2025 16:33:35 +0100 (CET) Received: from localhost (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Feb 2025 16:33:35 +0100 From: Christian Bruel To: , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v5 0/9] Add STM32MP25 PCIe drivers Date: Mon, 24 Feb 2025 16:33:04 +0100 Message-ID: <20250224153313.3416318-1-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_06,2025-02-24_02,2024-11-22_01 Changes in v5: Address driver comments from Manivanna: - Use dw_pcie_{suspend/resume}_noirq instead of private ones. - Move dw_pcie_host_init() to probe - Add stm32_remove_pcie_port cleanup function - Use of_node_put in stm32_pcie_parse_port - Remove wakeup-source property - Use generic dev_pm_set_dedicated_wake_irq to support wake# irq Changes in v4: Address bindings comments Rob Herring - Remove phy property form common yaml - Remove phy-name property - Move wake_gpio and reset_gpio to the host root port Changes in v3: Address comments from Manivanna, Rob and Bjorn: - Move host wakeup helper to dwc core (Mani) - Drop num-lanes=<1> from bindings (Rob) - Fix PCI address of I/O region (Mani) - Moved PHY to a RC rootport subsection (Bjorn, Mani) - Replaced dma-limit quirk by dma-ranges property (Bjorn) - Moved out perst assert/deassert from start/stop link (Mani) - Drop link_up test optim (Mani) - DT and comments rephrasing (Bjorn) - Add dts entries now that the combophy entries has landed - Drop delaying Configuration Requests Changes in v2: - Fix st,stm32-pcie-common.yaml dt_binding_check Changes in v1: Address comments from Rob Herring and Bjorn Helgaas: - Drop st,limit-mrrs and st,max-payload-size from this patchset - Remove single reset and clocks binding names and misc yaml cleanups - Split RC/EP common bindings to a separate schema file - Use correct PCIE_T_PERST_CLK_US and PCIE_T_RRS_READY_MS defines - Use .remove instead of .remove_new - Fix bar reset sequence in EP driver - Use cleanup blocks for error handling - Cosmetic fixes Christian Bruel (9): dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings PCI: stm32: Add PCIe host support for STM32MP25 dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings PCI: stm32: Add PCIe Endpoint support for STM32MP25 MAINTAINERS: add entry for ST STM32MP25 PCIe drivers arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi arm64: dts: st: Add PCIe Rootcomplex mode on stm32mp251 arm64: dts: st: Add PCIe Endpoint mode on stm32mp251 arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board .../bindings/pci/st,stm32-pcie-common.yaml | 33 ++ .../bindings/pci/st,stm32-pcie-ep.yaml | 67 +++ .../bindings/pci/st,stm32-pcie-host.yaml | 112 +++++ MAINTAINERS | 7 + arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 20 + arch/arm64/boot/dts/st/stm32mp251.dtsi | 58 ++- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 + drivers/pci/controller/dwc/Kconfig | 24 + drivers/pci/controller/dwc/Makefile | 2 + drivers/pci/controller/dwc/pcie-stm32-ep.c | 420 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.c | 367 +++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 16 + 12 files changed, 1146 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml create mode 100644 drivers/pci/controller/dwc/pcie-stm32-ep.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h