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Sat, 15 Mar 2025 21:09:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFLjlxYTdfNJqZhkesiYkuM2USBpUWsehzb+9Jry9ZoBFoQZCtcy0jiQ5jO8MhOA4QR3Rnwew== X-Received: by 2002:a17:90b:2dc4:b0:2f5:88bb:12f with SMTP id 98e67ed59e1d1-30151cab3ebmr8484156a91.21.1742098153973; Sat, 15 Mar 2025 21:09:13 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30153bc301esm3490438a91.49.2025.03.15.21.09.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Mar 2025 21:09:13 -0700 (PDT) From: Krishna Chaitanya Chundru Subject: [PATCH v8 0/4] PCI: dwc: Add support for configuring lane equalization presets Date: Sun, 16 Mar 2025 09:39:00 +0530 Message-Id: <20250316-preset_v6-v8-0-0703a78cb355@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIANxO1mcC/23MTQqDMBAF4KtI1o3khxjtqvcopaRmUgPV2MSGF vHuHV25EIaB92b4ZpIgekjkXMwkQvbJhwFDfSpI25nhCdRbzEQwoZjgjI4REkz3XFEO2qmKWS6 NJfiPF+e/m3W9Ye58mkL8bXSu1vZIwWG0fdhaasuYqO0lpFS+P+bVhr4vcZEVy3oHCLUHNAJGN dJJcLJR/ABYluUPZsdjOOoAAAA= To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru , Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, read the device tree property and stores in the presets structure. Based upon the lane width and supported data rate update lane equalization registers. This patch depends on the this dt binding pull request which got recently merged: https://github.com/devicetree-org/dt-schema/pull/146 Signed-off-by: Krishna Chaitanya Chundru --- Changes in v8: - Couple of nits by (bjorn & mani) - Add EQ_PRESET_8GTS by (mani). - Remove the logic not to update the DWC registers if the num_lanes is not equal to maximum lanes (mani) - Link to v7: https://lore.kernel.org/r/20250225-preset_v6-v7-0-a593f3ef3951@oss.qualcomm.com Changes in v7: - Update the 16bit array in the array (mani & konrad) - Update the couple of nits (comments, error log format etc) (mani) - remove !num_lanes check as this is not needed with this series (mani) - Add warning prints if the data rate is not supported and if there is no devicetree property for the data rate (mani). - Link to v6: https://lore.kernel.org/r/20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com Changes in v6: - update the dt properties to match the lane width ( mani & konard) - move everything to helper function and let the helper function determine reg size and offset (mani) - update the function header (mani) - move the num_lanes check to the main function (mani) - Link to v5: https://lore.kernel.org/linux-kernel/20250128-preset_v2-v5-0-4d230d956f8c@oss.qualcomm.com/ Changes in v5: - Instead of using of_property_present use return value of of_property_read_u8_array to know about property is present or not and add a macro for reserved value(Konrad). - Link to v4: https://lore.kernel.org/r/20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com Changes in v4: - use static arrays for storing preset values and use default value 0xff to indicate the property is not present (Dimitry & konrad). - Link to v3: https://lore.kernel.org/r/20241223-preset_v2-v3-0-a339f475caf5@oss.qualcomm.com Changes in v3: - In previous series a wrong patch was attached, correct it - Link to v2: https://lore.kernel.org/r/20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com Changes in v2: - Fix the kernel test robot error - As suggested by konrad use for loop and read "eq-presets-%ugts", (8 << i) - Link to v1: https://lore.kernel.org/r/20241116-presets-v1-0-878a837a4fee@quicinc.com --- Krishna Chaitanya Chundru (4): arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties PCI: of: Add of_pci_get_equalization_presets() API PCI: dwc: Update pci->num_lanes to maximum supported link width PCI: dwc: Add support for configuring lane equalization presets arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++++ drivers/pci/controller/dwc/pcie-designware-host.c | 63 +++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 8 +++ drivers/pci/controller/dwc/pcie-designware.h | 4 ++ drivers/pci/of.c | 44 ++++++++++++++++ drivers/pci/pci.h | 32 +++++++++++- include/uapi/linux/pci_regs.h | 3 ++ 7 files changed, 164 insertions(+), 1 deletion(-) --- base-commit: 3175967ecb3266d0ad7d2ca7ccceaf15fa2f15e2 change-id: 20250210-preset_v6-1e7f560d13ad Best regards,