[v9,0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file

Message

Dilip Kota Nov. 21, 2019, 9:31 a.m. UTC

Intel PCIe is Synopsys based controller. Intel PCIe driver uses
DesignWare PCIe framework for host initialization and register
configurations.

Dilip Kota (3):
  dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
  dwc: PCI: intel: PCIe RC controller driver
  PCI: artpec6: Configure FTS with dwc helper function

 .../devicetree/bindings/pci/intel-gw-pcie.yaml     | 138 ++++++
 drivers/pci/controller/dwc/Kconfig                 |  10 +
 drivers/pci/controller/dwc/Makefile                |   1 +
 drivers/pci/controller/dwc/pcie-artpec6.c          |   8 +-
 drivers/pci/controller/dwc/pcie-designware.c       |  57 +++
 drivers/pci/controller/dwc/pcie-designware.h       |  12 +
 drivers/pci/controller/dwc/pcie-intel-gw.c         | 545 +++++++++++++++++++++
 include/uapi/linux/pci_regs.h                      |   1 +
 8 files changed, 765 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
 create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c

Comments

Lorenzo Pieralisi Nov. 25, 2019, 5:03 p.m. UTC | #1

On Thu, Nov 21, 2019 at 05:31:17PM +0800, Dilip Kota wrote:
> Intel PCIe is Synopsys based controller. Intel PCIe driver uses
> DesignWare PCIe framework for host initialization and register
> configurations.
> 
> Dilip Kota (3):
>   dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
>   dwc: PCI: intel: PCIe RC controller driver

"PCI: dwc: ..."

You should follow other commit logs in history as a general
rule to make them uniform, I reordered it.

>   PCI: artpec6: Configure FTS with dwc helper function
> 
>  .../devicetree/bindings/pci/intel-gw-pcie.yaml     | 138 ++++++
>  drivers/pci/controller/dwc/Kconfig                 |  10 +
>  drivers/pci/controller/dwc/Makefile                |   1 +
>  drivers/pci/controller/dwc/pcie-artpec6.c          |   8 +-
>  drivers/pci/controller/dwc/pcie-designware.c       |  57 +++
>  drivers/pci/controller/dwc/pcie-designware.h       |  12 +
>  drivers/pci/controller/dwc/pcie-intel-gw.c         | 545 +++++++++++++++++++++
>  include/uapi/linux/pci_regs.h                      |   1 +
>  8 files changed, 765 insertions(+), 7 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
>  create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c

Applied to pci/dwc, we should be able to merge it for v5.5.

Lorenzo

Dilip Kota Nov. 26, 2019, 10:03 a.m. UTC | #2

On 11/26/2019 1:03 AM, Lorenzo Pieralisi wrote:
> On Thu, Nov 21, 2019 at 05:31:17PM +0800, Dilip Kota wrote:
>> Intel PCIe is Synopsys based controller. Intel PCIe driver uses
>> DesignWare PCIe framework for host initialization and register
>> configurations.
>>
>> Dilip Kota (3):
>>    dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
>>    dwc: PCI: intel: PCIe RC controller driver
> "PCI: dwc: ..."
>
> You should follow other commit logs in history as a general
Sure Noted.
> rule to make them uniform, I reordered it.
Thank you,
>
>>    PCI: artpec6: Configure FTS with dwc helper function
>>
>>   .../devicetree/bindings/pci/intel-gw-pcie.yaml     | 138 ++++++
>>   drivers/pci/controller/dwc/Kconfig                 |  10 +
>>   drivers/pci/controller/dwc/Makefile                |   1 +
>>   drivers/pci/controller/dwc/pcie-artpec6.c          |   8 +-
>>   drivers/pci/controller/dwc/pcie-designware.c       |  57 +++
>>   drivers/pci/controller/dwc/pcie-designware.h       |  12 +
>>   drivers/pci/controller/dwc/pcie-intel-gw.c         | 545 +++++++++++++++++++++
>>   include/uapi/linux/pci_regs.h                      |   1 +
>>   8 files changed, 765 insertions(+), 7 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
>>   create mode 100644 drivers/pci/controller/dwc/pcie-intel-gw.c
> Applied to pci/dwc, we should be able to merge it for v5.5.

Thank you.

Regards,
Dilip

>
> Lorenzo