From patchwork Fri Jun 7 09:24:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 2685671 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id D59733FC23 for ; Fri, 7 Jun 2013 09:24:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752185Ab3FGJYM (ORCPT ); Fri, 7 Jun 2013 05:24:12 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:11627 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751202Ab3FGJYK (ORCPT ); Fri, 7 Jun 2013 05:24:10 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MO0007HRNG8AER0@mailout1.samsung.com>; Fri, 07 Jun 2013 18:24:08 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.48]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id A3.92.03969.8B6A1B15; Fri, 07 Jun 2013 18:24:08 +0900 (KST) X-AuditID: cbfee68f-b7f436d000000f81-fa-51b1a6b81c9a Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id B3.2E.28381.7B6A1B15; Fri, 07 Jun 2013 18:24:07 +0900 (KST) Received: from DOJG1HAN03 ([12.23.120.99]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MO000GXWNG7P9I0@mmp2.samsung.com>; Fri, 07 Jun 2013 18:24:07 +0900 (KST) From: Jingoo Han To: 'Kukjin Kim' , 'Bjorn Helgaas' Cc: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 'Grant Likely' , 'Andrew Murray' , 'Thomas Petazzoni' , 'Thierry Reding' , 'Jason Gunthorpe' , 'Surendranath Gurivireddy Balla' , 'Siva Reddy Kallam' , 'Thomas Abraham' , Jingoo Han Subject: [PATCH V3 3/3] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC Date: Fri, 07 Jun 2013 18:24:07 +0900 Message-id: <000f01ce6360$c29c3370$47d49a50$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Outlook 14.0 Thread-index: Ac5jYLu3azxp7/LgQ5CrQ8n775Wo8A== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEKsWRmVeSWpSXmKPExsVy+t8zA90dyzYGGszcwGLR/H87q8WSpgyL A7Mfslq8OrORzeLywkusFt9vmFr0LrjKZrHp8TVWi8u75rBZnJ13nM1ixvl9TBYrmrYyWiy+ uJzZYvfKJSwWx2YsYbR4+qCJyUHAY828NYwefVOusnk82XSR0WPBplKPO9f2sHlsXlLvcX7G QkaP7zt6gQq2rGL0+PlSx+PzJrkA7igum5TUnMyy1CJ9uwSujCczWlgLbgpUTH1/k7mBcTZv FyMnh4SAicTKtW/ZIWwxiQv31rN1MXJxCAksY5SY3nmGGabozo1JTBCJ6YwSv87tYYRwfjFK zDzxEqydTUBN4suXw2C2iIC/xLWrrSwgRcwC71kkbv/YxwqSEBYIl3gzaQvYWBYBVYlTB96x gNi8ApYS0/ZvZ4WwBSV+TL4HFmcW0JJYv/M4E4QtL7F5zVuokxQkdpx9zQixTE/i0cd5jBA1 IhL7XrwDu05CYA+HREPfJ1aIZQIS3yYfAhrKAZSQldh0AGqOpMTBFTdYJjCKzUKyehaS1bOQ rJ6FZMUCRpZVjKKpBckFxUnpRcZ6xYm5xaV56XrJ+bmbGCHpoX8H490D1ocYk4HWT2SWEk3O B6aXvJJ4Q2MzIwtTE1NjI3NLM9KElcR51VqsA4UE0hNLUrNTUwtSi+KLSnNSiw8xMnFwSjUw BiioTJLae/Ppr8J3U85bv1jQ5vw72f1r0RrmS8Exb4+ZXWy/K5OwfJlkRp1DqlNzeO/xB6yv 5Y3X7WOXeZK/JepGUJMda/xGBdvn+ex5XBOzf/GGiSv8d17TUH61Sj5vZ29SXFmwsY3hmxiT f/xfLjlNnFO/QNVT14kji2XV/i3Pfrd8c/RTYinOSDTUYi4qTgQA3vWlEyUDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPKsWRmVeSWpSXmKPExsVy+t9jQd3tyzYGGvy/YW3R/H87q8WSpgyL A7Mfslq8OrORzeLywkusFt9vmFr0LrjKZrHp8TVWi8u75rBZnJ13nM1ixvl9TBYrmrYyWiy+ uJzZYvfKJSwWx2YsYbR4+qCJyUHAY828NYwefVOusnk82XSR0WPBplKPO9f2sHlsXlLvcX7G QkaP7zt6gQq2rGL0+PlSx+PzJrkA7qgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11D SwtzJYW8xNxUWyUXnwBdt8wcoG+UFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqGBMH1GBmg gYR1jBlPZrSwFtwUqJj6/iZzA+Ns3i5GTg4JAROJOzcmMUHYYhIX7q1n62Lk4hASmM4o8evc HkYI5xejxMwTL9lBqtgE1CS+fDkMZosI+Etcu9rKAlLELPCeReL2j32sIAlhgXCJN5O2MIPY LAKqEqcOvGMBsXkFLCWm7d/OCmELSvyYfA8sziygJbF+53EmCFteYvOat8wQJylI7Dj7mhFi mZ7Eo4/zGCFqRCT2vXjHOIFRYBaSUbOQjJqFZNQsJC0LGFlWMYqmFiQXFCel5xrqFSfmFpfm pesl5+duYgQnn2dSOxhXNlgcYhTgYFTi4f25akOgEGtiWXFl7iFGCQ5mJRHel7M2BgrxpiRW VqUW5ccXleakFh9iTAb6dCKzlGhyPjAx5pXEGxqbmBlZGplZGJmYm5MmrCTOe6DVOlBIID2x JDU7NbUgtQhmCxMHp1QDY8ap+bPf17P9stLj5ZtZmrnfWOV4eAND2ISKBzcKf7C6xZ4T/H+8 O+dZ+mKO9LfKtvKsZmGut1JfPKv9XBO958b91WW7txlmz9fWkX4SX6SfYLE5Nc34ppVJwet1 E37MEH5/YsdiFvZ/QovmOe5kul91TWB7HbtVVmr/xROPRX5Xp74tnajcoMRSnJFoqMVcVJwI AImzO3KCAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Exynos5440 has two PCIe controllers which can be used as root complex for PCIe interface. Signed-off-by: Jingoo Han --- arch/arm/boot/dts/exynos5440-ssdk5440.dts | 8 ++++++++ arch/arm/boot/dts/exynos5440.dtsi | 32 +++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index d55042b..efe7d39 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -30,4 +30,12 @@ clock-frequency = <50000000>; }; }; + + pcie0@40000000 { + reset-gpio = <5>; + }; + + pcie1@60000000 { + reset-gpio = <22>; + }; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index f6b1c89..ea37e94 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -216,4 +216,36 @@ clock-names = "rtc"; status = "disabled"; }; + + pcie0@40000000 { + compatible = "samsung,exynos5440-pcie"; + reg = <0x40000000 0x4000 + 0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xf>; + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00200000 /* configuration space */ + 0x81000000 0 0 0x40200000 0 0x00004000 /* downstream I/O */ + 0x82000000 0 0 0x40204000 0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie1@60000000 { + compatible = "samsung,exynos5440-pcie"; + reg = <0x60000000 0x4000 + 0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xf>; + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00200000 /* configuration space */ + 0x81000000 0 0 0x60200000 0 0x00004000 /* downstream I/O */ + 0x82000000 0 0 0x60204000 0 0x10000000>; /* non-prefetchable memory */ + }; };