From patchwork Tue Dec 10 07:02:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 3314621 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 080AA9F37C for ; Tue, 10 Dec 2013 07:02:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB1212034F for ; Tue, 10 Dec 2013 07:02:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 82A7D20340 for ; Tue, 10 Dec 2013 07:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750787Ab3LJHCi (ORCPT ); Tue, 10 Dec 2013 02:02:38 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:16213 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750754Ab3LJHCh (ORCPT ); Tue, 10 Dec 2013 02:02:37 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MXK00K40WWBL3E0@mailout2.samsung.com> for linux-pci@vger.kernel.org; Tue, 10 Dec 2013 16:02:35 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.50]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 0D.C6.15387.B8CB6A25; Tue, 10 Dec 2013 16:02:35 +0900 (KST) X-AuditID: cbfee68f-b7f256d000003c1b-73-52a6bc8b7d13 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 5E.4F.17171.B8CB6A25; Tue, 10 Dec 2013 16:02:35 +0900 (KST) Received: from DOJG1HAN03 ([12.23.120.99]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MXK00E95WWASG40@mmp1.samsung.com>; Tue, 10 Dec 2013 16:02:34 +0900 (KST) From: Jingoo Han To: 'Marek Vasut' , 'Richard Zhu' Cc: 'Mohit KUMAR DCG' , 'Pratyush ANAND' , 'Arnd Bergmann' , 'Kishon Vijay Abraham I' , linux-pci@vger.kernel.org, 'Tim Harvey' , 'Jingoo Han' References: <20131205050424.GA2298@pratyush-vbox> <201312061546.23981.arnd@arndb.de> <20131209071241.GA5760@pratyush-vbox> <201312091709.38013.arnd@arndb.de> <20131210043409.GA2734@pratyush-vbox> <000101cef568$3cd0e4d0$b672ae70$%han@samsung.com> <2CC2A0A4A178534D93D5159BF3BCB66189F9536CE2@EAPEX1MAIL1.st.com> In-reply-to: <2CC2A0A4A178534D93D5159BF3BCB66189F9536CE2@EAPEX1MAIL1.st.com> Subject: Re: [Query/Discussion]: IO translation with designware PCIe controller Date: Tue, 10 Dec 2013 16:02:34 +0900 Message-id: <001201cef575$cd4fc960$67ef5c20$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac71YR2+1Np7mBEZSjC49pG6xtNZOwABokHgAAJG5MAAAP8PkA== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPIsWRmVeSWpSXmKPExsVy+t8zI93uPcuCDHa3S1n8nXSM3eLlIU2L D8/Xs1hcXniJ1eLC0x42i7PzjrNZvGlrZLTYOPUXo0X7JWWLiyc+MTtwefz+NYnRY96sEywe /w73M3mc67nL5tG3ZRWjx9Mfe5k9jt/YzuTxeZNcAEcUl01Kak5mWWqRvl0CV8b0HzvZCubq VVxra2JvYFyv3MXIySEhYCKxrncZM4QtJnHh3nq2LkYuDiGBZYwSe29/ZoQp+nr3NDNEYhGj RH/jcyaQhJDAL0aJxq1mIDabgJrEly+H2UFsEQE/iUcPO1hBGpgFupgkbj/bwA7RvZdJ4u3d NrB9nAI+EnvblrCC2MIC/hLdr6aDxVkEVCU+HH0JtoFXwFbi89eNbBC2oMSPyfdYQGxmAS2J 9TuPM0HY8hKb17wF6uUAOlVd4tFfXYgjnCTaz75ihygRkdj34h0jyA0SAjM5JK5vaGOE2CUg 8W3yIRaIXlmJTQegQSEpcXDFDZYJjBKzkGyehWTzLCSbZyFZsYCRZRWjaGpBckFxUnqRsV5x Ym5xaV66XnJ+7iZGSOT372C8e8D6EGMy0PqJzFKiyfnAxJFXEm9obGZkYWpiamxkbmlGmrCS OO/9h0lBQgLpiSWp2ampBalF8UWlOanFhxiZODilGhjzPpz+IPPvrYjowSc2HyYpppXdPi/Y t+3b5+m5Bz4mW2bqpGvZfHnvHuEs9nDjP6vWV987/9618zqo1PTQ6ry378nswMhNBbMy2nxd ftkf9s3fMYv12YnlQVsvcdQHx/Eq6b22PmNtsGaaxkKDq1wvu+Rkg7Kmv61+r7Fqs9Ep3c0x xQpZvPJKLMUZiYZazEXFiQBY7wyjEgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrDKsWRmVeSWpSXmKPExsVy+t9jAd3uPcuCDFqWilj8nXSM3eLlIU2L D8/Xs1hcXniJ1eLC0x42i7PzjrNZvGlrZLTYOPUXo0X7JWWLiyc+MTtwefz+NYnRY96sEywe /w73M3mc67nL5tG3ZRWjx9Mfe5k9jt/YzuTxeZNcAEdUA6NNRmpiSmqRQmpecn5KZl66rZJ3 cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtCNSgpliTmlQKGAxOJiJX07TBNCQ9x0LWAa I3R9Q4LgeowM0EDCOsaM6T92shXM1au41tbE3sC4XrmLkZNDQsBE4uvd08wQtpjEhXvr2boY uTiEBBYxSvQ3PmcCSQgJ/GKUaNxqBmKzCahJfPlymB3EFhHwk3j0sIMVpIFZoItJ4vazDewQ 3XuZJN7ebQMbyyngI7G3bQkriC0s4C/R/Wo6WJxFQFXiw9GXYBt4BWwlPn/dyAZhC0r8mHyP BcRmFtCSWL/zOBOELS+xec1boF4OoFPVJR791YU4wkmi/ewrdogSEYl9L94xTmAUmoVk0iwk k2YhmTQLScsCRpZVjKKpBckFxUnpuYZ6xYm5xaV56XrJ+bmbGMFp5ZnUDsaVDRaHGAU4GJV4 eAsYlgUJsSaWFVfmHmKU4GBWEuH1rAMK8aYkVlalFuXHF5XmpBYfYkwGenQis5Rocj4w5eWV xBsam5gZWRqZWRiZmJuTJqwkznug1TpQSCA9sSQ1OzW1ILUIZgsTB6dUA2Pt/+zbijwZzy4F C//9smwJf2iN8LZiJzMnt9lXFz6b08JxSDy/dMe5FVOlXj+OPaa37eB1tu35etFN/5qKDWJS J2VMKk4q07iw73RQ8j6b+9W6xy7qiBbKKIo77ntdt3TxPu3naraTD2/ckvXfv3fOhukG8xa1 hda2z5iWxyt+mM9v5ZPixe+VWIozEg21mIuKEwH8W1KfbwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tuesday, December 10, 2013 3:31 PM, Mohit KUMAR DCG wrote: > On Tuesday, December 10, 2013 10:55 AM, Jingoo Han wrote: > > On Tuesday, December 10, 2013 1:34 PM, Pratyush Anand wrote: > > > On Tue, Dec 10, 2013 at 12:09:37AM +0800, Arnd Bergmann wrote: > > > > On Monday 09 December 2013, Pratyush Anand wrote: > > > > > > I think it does handle this correctly, look at > > > > > > > > > > > > static int dw_pcie_setup(int nr, struct pci_sys_data *sys) { > > > > > > ... > > > > > > if (global_io_offset < SZ_1M && pp->config.io_size > 0) { > > > > > > sys->io_offset = global_io_offset - pp->config.io_bus_addr; > > > > > > pci_ioremap_io(sys->io_offset, pp->io.start); > > > > > > global_io_offset += SZ_64K; > > > > > > pci_add_resource_offset(&sys->resources, &pp->io, > > > > > > sys->io_offset); > > > > > > } > > > > > > ... > > > > > > } > > > > > > > > > > > > I believe this does the right thing, but you have to put the > > > > > > correct translation into the 'ranges' property of the host bridge node > > in DT. > > > > > > > > > > May be not exactly. pp->io is the realio, and it is passed > > > > > correctly to pci_add_resource_offset. But, as you had also said > > > > > that pci_ioremap_io will receive cpu physical address space as > > > > > input, therefore I think following modification will be needed to > > > > > work io transaction properly. > > > > > > > > I see. I think you are right. > > > > > > > > > diff --git a/drivers/pci/host/pcie-designware.c > > > > > b/drivers/pci/host/pcie-designware.c > > > > > index be6ce30..cf68632 100644 > > > > > --- a/drivers/pci/host/pcie-designware.c > > > > > +++ b/drivers/pci/host/pcie-designware.c > > > > > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port > > *pp) > > > > > + global_io_offset); > > > > > pp->config.io_size = resource_size(&pp->io); > > > > > pp->config.io_bus_addr = range.pci_addr; > > > > > + pp->io_base = range.cpu_addr; > > > > > } > > > > > if (restype == IORESOURCE_MEM) { > > > > > of_pci_range_to_resource(&range, np, &pp->mem); > > @@ -403,7 > > > > > +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) > > > > > > > > > > pp->cfg0_base = pp->cfg.start; > > > > > pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; > > > > > - pp->io_base = pp->io.start; > > > > > pp->mem_base = pp->mem.start; > > > > > > > > > > pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, > > > > > > > > This looks correct to me and it seems to also fix a bug in > > > > dw_pcie_prog_viewport_io_outbound if I read this correctly. > > > > > > Yes, now outbound viewport for IO translation will get correct input > > > address. > > > > > > > > > > > > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct > > > > > pci_sys_data *sys) > > > > > > > > > > if (global_io_offset < SZ_1M && pp->config.io_size > 0) { > > > > > sys->io_offset = global_io_offset - pp->config.io_bus_addr; > > > > > - pci_ioremap_io(sys->io_offset, pp->io.start); > > > > > + pci_ioremap_io(sys->io_offset, pp->io_base); > > > > > global_io_offset += SZ_64K; > > > > > pci_add_resource_offset(&sys->resources, &pp->io, > > > > > sys->io_offset); > > > > > > > > I think there is still a related bug in here: we should pass > > > > global_io_offset rather than sys->io_offset to pci_ioremap_io, so we > > > > map the new window into the first available spot in the Linux view > > > > of the I/O space, rather than passing a number that might be zero > > > > for any bus, if the 'ranges' are set up to have an identity mapping > > > > between Linux I/O spaces and PCI I/O spaces. You should be able to > > > > verify this by setting the I/O range for the bus to a random 4KB > > > > multiple in DT and observe that Linux start allocating ports from 0x1000 > > but the raw BAR values would contain the value you have chosen. > > > > > > OK. > > > > > > @ Jingoo, Mohit > > - Now its working properly for SPEAr1310 tested with directly connected EP(xhc cards) as well as EP > Connected through switch(Lecroy PTC in AIC mode). Without this patch my EP devices were not working > when > connected through Switch. Hi Marek, Richard, How about testing the following Pratyush's patch on imx6 platform with the Pericom PI7C9X2G303EL PCIe switch? As Mohit tested, it looks to resolve the i.MX6 problem when the PCIe switch is connected to the i.MX6 platform. Best regards, Jingoo Han [.....] --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index be6ce30..b83f5e8 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) + global_io_offset); pp->config.io_size = resource_size(&pp->io); pp->config.io_bus_addr = range.pci_addr; + pp->io_base = range.cpu_addr; } if (restype == IORESOURCE_MEM) { of_pci_range_to_resource(&range, np, &pp->mem); @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = pp->cfg.start; pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; - pp->io_base = pp->io.start; pp->mem_base = pp->mem.start; pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) if (global_io_offset < SZ_1M && pp->config.io_size > 0) { sys->io_offset = global_io_offset - pp->config.io_bus_addr; - pci_ioremap_io(sys->io_offset, pp->io.start); + pci_ioremap_io(global_io_offset, pp->io_base); global_io_offset += SZ_64K; pci_add_resource_offset(&sys->resources, &pp->io, sys->io_offset);