From patchwork Fri Sep 6 08:21:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 2854434 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3FE11C0AB5 for ; Fri, 6 Sep 2013 08:21:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D68072029B for ; Fri, 6 Sep 2013 08:21:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 059272026F for ; Fri, 6 Sep 2013 08:21:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750958Ab3IFIVu (ORCPT ); Fri, 6 Sep 2013 04:21:50 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:18229 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750941Ab3IFIVs (ORCPT ); Fri, 6 Sep 2013 04:21:48 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MSP006QX37M2PK0@mailout4.samsung.com>; Fri, 06 Sep 2013 17:21:45 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.49]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 69.4D.22755.99099225; Fri, 06 Sep 2013 17:21:45 +0900 (KST) X-AuditID: cbfee68f-b7f656d0000058e3-57-5229909913d6 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id C9.1E.09055.99099225; Fri, 06 Sep 2013 17:21:45 +0900 (KST) Received: from DOJG1HAN03 ([12.23.120.99]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MSP00JIS389OO90@mmp2.samsung.com>; Fri, 06 Sep 2013 17:21:45 +0900 (KST) From: Jingoo Han To: 'Bjorn Helgaas' Cc: linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, 'Kukjin Kim' , 'Jingoo Han' Subject: [PATCH] PCI: exynos: turn off power of phy block when link failed Date: Fri, 06 Sep 2013 17:21:45 +0900 Message-id: <002301ceaada$1ffa8fb0$5fefaf10$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac6q2h/c8nlkthLmRlmduX+VKgn6+A== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKIsWRmVeSWpSXmKPExsVy+t8zQ92ZEzSDDJb/NrJY0pRhcXnhJVaL 3gVX2SzOzjvOZjHj/D4mB1aPBZtKPfq2rGL0+LxJLoA5issmJTUnsyy1SN8ugSvj9Zl9jAVf lCqeHp3B1sB4XbaLkZNDQsBEYunrfSwQtpjEhXvr2boYuTiEBJYxSpz4dIMdpmjO9ucsEInp jBKvnyyGcn4xSnTcOskMUsUmoCbx5cthsA4RAU2J2Su2MIEUMQv0MEo0L9oPtkNYwEti6dcf YEUsAqoSfz6fBLN5BWwljh3fxAhhC0r8mHwPrJ5ZQEti/c7jTBC2vMTmNW+BlnEAnaQu8eiv LsQuPYktszdAlYhI7HvxjhFkr4TAJnaJP/8aWSF2CUh8m3yIBaJXVmLTAWaIzyQlDq64wTKB UWwWks2zkGyehWTzLCQrFjCyrGIUTS1ILihOSi8y1itOzC0uzUvXS87P3cQIibL+HYx3D1gf YkwGWj+RWUo0OR8YpXkl8YbGZkYWpiamxkbmlmakCSuJ86q1WAcKCaQnlqRmp6YWpBbFF5Xm pBYfYmTi4JRqYCw5Vv+x33+HR9pPywk67f1q5jsOr9n8bkna0VmHu8wE25kZZQpzLz+7ar/w V4fOst9Z+UvXy/qnfWmyLT836XTZFbeXymln7vcyf1CYbP//27EJZ5PXzxc8zv08VFBBVWl2 iSaLxZpPas33P1U6+xjPWmNkwr9Ho0z0vsBa39fvHt0L5V72brcSS3FGoqEWc1FxIgCOxhww yAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEKsWRmVeSWpSXmKPExsVy+t9jQd2ZEzSDDP626VksacqwuLzwEqtF 74KrbBZn5x1ns5hxfh+TA6vHgk2lHn1bVjF6fN4kF8Ac1cBok5GamJJapJCal5yfkpmXbqvk HRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIToOuWmQO0UUmhLDGnFCgUkFhcrKRvh2lCaIibrgVM Y4Sub0gQXI+RARpIWMeY8frMPsaCL0oVT4/OYGtgvC7bxcjJISFgIjFn+3MWCFtM4sK99Wxd jFwcQgLTGSVeP1nMAuH8YpTouHWSGaSKTUBN4suXw+wgtoiApsTsFVuYQIqYBXoYJZoX7Qcb JSzgJbH06w+wIhYBVYk/n0+C2bwCthLHjm9ihLAFJX5MvgdWzyygJbF+53EmCFteYvOat0DL OIBOUpd49FcXYpeexJbZG6BKRCT2vXjHOIFRYBaSSbOQTJqFZNIsJC0LGFlWMYqmFiQXFCel 5xrqFSfmFpfmpesl5+duYgTH8DOpHYwrGywOMQpwMCrx8HL0aAQJsSaWFVfmHmKU4GBWEuEV 19AMEuJNSaysSi3Kjy8qzUktPsSYDPToRGYp0eR8YHrJK4k3NDYxM7I0MrMwMjE3J01YSZz3 QKt1oJBAemJJanZqakFqEcwWJg5OqQZGvjNzjnuwic1ZLekf5m6dtUigt8+3zMeTXcw5/r2g 3DarrNo4tSm7z/Qu0HWJvPOy6eTsGD5H9vTp4YXRK3jOnDq+aUnNZod1ezsy0zo1W7KFt3+Q V0mzfb6rZI/x/xm5H75pFskm2zuv+BhY8+2k/x2uH0El/SvqG4qYe37fPPe7dq0EL4sSS3FG oqEWc1FxIgAEOOaHJQMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When link failed, there is no need to turn on phy block. Also, turning on phy block is added, in order to turn on phy block regardless of the default value of phy registers. Signed-off-by: Jingoo Han --- Tested on Exynos5440. drivers/pci/host/pci-exynos.c | 68 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 94e096b..974f091 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -77,18 +77,28 @@ struct exynos_pcie { #define PCIE_PHY_PLL_BIAS 0x00c #define PCIE_PHY_DCC_FEEDBACK 0x014 #define PCIE_PHY_PLL_DIV_1 0x05c +#define PCIE_PHY_COMMON_POWER 0x064 +#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3) #define PCIE_PHY_TRSV0_EMP_LVL 0x084 #define PCIE_PHY_TRSV0_DRV_LVL 0x088 #define PCIE_PHY_TRSV0_RXCDR 0x0ac +#define PCIE_PHY_TRSV0_POWER 0x0c4 +#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV0_LVCC 0x0dc #define PCIE_PHY_TRSV1_EMP_LVL 0x144 #define PCIE_PHY_TRSV1_RXCDR 0x16c +#define PCIE_PHY_TRSV1_POWER 0x184 +#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV1_LVCC 0x19c #define PCIE_PHY_TRSV2_EMP_LVL 0x204 #define PCIE_PHY_TRSV2_RXCDR 0x22c +#define PCIE_PHY_TRSV2_POWER 0x244 +#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV2_LVCC 0x25c #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 #define PCIE_PHY_TRSV3_RXCDR 0x2ec +#define PCIE_PHY_TRSV3_POWER 0x304 +#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV3_LVCC 0x31c static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) @@ -202,6 +212,58 @@ static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET); } +static void exynos_pcie_power_on_phy(struct pcie_port *pp) +{ + u32 val; + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); + val &= ~PCIE_PHY_COMMON_PD_CMN; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); + val &= ~PCIE_PHY_TRSV0_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); + val &= ~PCIE_PHY_TRSV1_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); + val &= ~PCIE_PHY_TRSV2_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); + val &= ~PCIE_PHY_TRSV3_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); +} + +static void exynos_pcie_power_off_phy(struct pcie_port *pp) +{ + u32 val; + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); + val |= PCIE_PHY_COMMON_PD_CMN; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); + val |= PCIE_PHY_TRSV0_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); + val |= PCIE_PHY_TRSV1_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); + val |= PCIE_PHY_TRSV2_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); + val |= PCIE_PHY_TRSV3_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); +} + static void exynos_pcie_init_phy(struct pcie_port *pp) { struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); @@ -270,6 +332,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) /* de-assert phy reset */ exynos_pcie_deassert_phy_reset(pp); + /* power on phy */ + exynos_pcie_power_on_phy(pp); + /* initialize phy */ exynos_pcie_init_phy(pp); @@ -302,6 +367,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) PCIE_PHY_PLL_LOCKED); dev_info(pp->dev, "PLL Locked: 0x%x\n", val); } + /* power off phy */ + exynos_pcie_power_off_phy(pp); + dev_err(pp->dev, "PCIe Link Fail\n"); return -EINVAL; }