From patchwork Fri Jun 26 02:45:35 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Zhao X-Patchwork-Id: 32501 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n5Q2jNqI021371 for ; Fri, 26 Jun 2009 02:45:23 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751893AbZFZCpR (ORCPT ); Thu, 25 Jun 2009 22:45:17 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752101AbZFZCpR (ORCPT ); Thu, 25 Jun 2009 22:45:17 -0400 Received: from mga11.intel.com ([192.55.52.93]:12163 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751893AbZFZCpQ (ORCPT ); Thu, 25 Jun 2009 22:45:16 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 25 Jun 2009 19:37:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.42,294,1243839600"; d="scan'208";a="702658737" Received: from yzhao-otc.sh.intel.com ([10.239.48.81]) by fmsmga001.fm.intel.com with ESMTP; 25 Jun 2009 19:48:41 -0700 From: Yu Zhao To: mj@ucw.cz Cc: linux-pci@vger.kernel.org, Yu Zhao Subject: [PATCH 1/2] PCIUtiles: support PCI Advanced Features capability Date: Fri, 26 Jun 2009 10:45:35 +0800 Message-Id: <1245984336-1885-1-git-send-email-yu.zhao@intel.com> X-Mailer: git-send-email 1.6.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The capability is defined by http://www.pcisig.com/specifications/conventional/pci_30/ECN_Conventional_Adv_Caps_27Jul06.pdf Signed-off-by: Yu Zhao --- lib/header.h | 9 +++++++++ ls-caps.c | 22 ++++++++++++++++++++-- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/lib/header.h b/lib/header.h index ec34f44..8911c17 100644 --- a/lib/header.h +++ b/lib/header.h @@ -871,6 +871,15 @@ #define PCI_SSVID_VENDOR 4 #define PCI_SSVID_DEVICE 6 +/* PCI Advanced Features */ +#define PCI_AF_CAP 3 +#define PCI_AF_CAP_TP 0x01 +#define PCI_AF_CAP_FLR 0x02 +#define PCI_AF_CTRL 4 +#define PCI_AF_CTRL_FLR 0x01 +#define PCI_AF_STATUS 5 +#define PCI_AF_STATUS_TP 0x01 + /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */ diff --git a/ls-caps.c b/ls-caps.c index 3e01f2c..fb20ac0 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -1146,6 +1146,24 @@ cap_debug_port(int cap) printf("Debug port: BAR=%d offset=%04x\n", bar, pos); } +static void +cap_af(struct device *d, int where) +{ + u8 reg; + + printf("PCI Advanced Features\n"); + if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3)) + return; + + reg = get_conf_byte(d, where + PCI_AF_CAP); + printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP), + FLAG(reg, PCI_AF_CAP_FLR)); + reg = get_conf_byte(d, where + PCI_AF_CTRL); + printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR)); + reg = get_conf_byte(d, where + PCI_AF_STATUS); + printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP)); +} + void show_caps(struct device *d) { @@ -1207,7 +1225,7 @@ show_caps(struct device *d) cap_ht(d, where, cap); break; case PCI_CAP_ID_VNDR: - printf("Vendor Specific Information \n"); + printf("Vendor Specific Information\n"); break; case PCI_CAP_ID_DBG: cap_debug_port(cap); @@ -1238,7 +1256,7 @@ show_caps(struct device *d) printf("SATA HBA \n"); break; case PCI_CAP_ID_AF: - printf("PCIe advanced features \n"); + cap_af(d, where); break; default: printf("#%02x [%04x]\n", id, cap);