From patchwork Thu Sep 30 15:38:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Garrett X-Patchwork-Id: 220392 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o8UFd1T6006610 for ; Thu, 30 Sep 2010 15:39:02 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932156Ab0I3Piu (ORCPT ); Thu, 30 Sep 2010 11:38:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:4229 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932083Ab0I3Pit (ORCPT ); Thu, 30 Sep 2010 11:38:49 -0400 Received: from int-mx03.intmail.prod.int.phx2.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.16]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id o8UFcmfw010526 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 30 Sep 2010 11:38:48 -0400 Received: from cavan.codon.org.uk ([10.3.113.5]) by int-mx03.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id o8UFckch014226 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=NO); Thu, 30 Sep 2010 11:38:47 -0400 Received: from nat-pool-rdu.redhat.com ([66.187.233.202] helo=localhost.localdomain) by cavan.codon.org.uk with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1P1LDY-0003lp-6g; Thu, 30 Sep 2010 16:38:44 +0100 From: Matthew Garrett To: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org, joerg.roedel@amd.com, jbarnes@virtuousgeek.org, Matthew Garrett Subject: [PATCH] pci: Reenable the AMD IOMMU if it's mysteriously vanished over suspend Date: Thu, 30 Sep 2010 11:38:28 -0400 Message-Id: <1285861108-24122-1-git-send-email-mjg@redhat.com> X-SA-Do-Not-Run: Yes X-SA-Exim-Connect-IP: 66.187.233.202 X-SA-Exim-Mail-From: mjg@redhat.com X-SA-Exim-Scanned: No (on cavan.codon.org.uk); SAEximRunCond expanded to false X-Scanned-By: MIMEDefang 2.67 on 10.5.11.16 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 30 Sep 2010 15:39:02 +0000 (UTC) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 89ed181..dcf9832 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2695,6 +2695,39 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, #endif /*CONFIG_MMC_RICOH_MMC*/ +#ifdef CONFIG_AMD_IOMMU + +/* Some AMD BIOSes fail to reenable the iommu on resume */ + +static void amd_iommu_reenable(struct pci_dev *dev) +{ + u32 ioc_feature_control; + struct pci_dev *iommu; + + iommu = pci_get_device(PCI_VENDOR_ID_ATI, 0x5a23, NULL); + + if (!iommu) + return; + + /* Select Northbridge indirect register 0x75 and enable writing */ + pci_write_config_dword(dev, 0x60, 0x75 | (1 << 7)); + pci_read_config_dword(dev, 0x64, &ioc_feature_control); + + /* Enable the iommu if it's vanished */ + if (!(ioc_feature_control & 0x1)) + pci_write_config_dword(dev, 0x64, ioc_feature_control | 1); + + /* Disable writing again */ + pci_write_config_dword(dev, 0x60, 0x75); + + pci_dev_put(iommu); +} + +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x5a10, amd_iommu_reenable); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x5a12, amd_iommu_reenable); +DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x5a13, amd_iommu_reenable); +#endif + static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) {