From patchwork Mon Apr 11 09:32:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joerg Roedel X-Patchwork-Id: 697831 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3B9Wp7Y007317 for ; Mon, 11 Apr 2011 09:32:51 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755016Ab1DKJcO (ORCPT ); Mon, 11 Apr 2011 05:32:14 -0400 Received: from tx2ehsobe002.messaging.microsoft.com ([65.55.88.12]:55472 "EHLO TX2EHSOBE003.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754990Ab1DKJcM (ORCPT ); Mon, 11 Apr 2011 05:32:12 -0400 Received: from mail178-tx2-R.bigfish.com (10.9.14.250) by TX2EHSOBE003.bigfish.com (10.9.40.23) with Microsoft SMTP Server id 14.1.225.8; Mon, 11 Apr 2011 09:32:10 +0000 Received: from mail178-tx2 (localhost.localdomain [127.0.0.1]) by mail178-tx2-R.bigfish.com (Postfix) with ESMTP id 9E3DFF4025F; Mon, 11 Apr 2011 09:32:10 +0000 (UTC) X-SpamScore: -2 X-BigFish: VPS-2(zzbb2cKzz1202hzz8275bhz32i668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:ausb3twp01.amd.com; RD:none; EFVD:NLI Received: from mail178-tx2 (localhost.localdomain [127.0.0.1]) by mail178-tx2 (MessageSwitch) id 1302514330178327_7289; Mon, 11 Apr 2011 09:32:10 +0000 (UTC) Received: from TX2EHSMHS021.bigfish.com (unknown [10.9.14.246]) by mail178-tx2.bigfish.com (Postfix) with ESMTP id 1EB304C8050; Mon, 11 Apr 2011 09:32:10 +0000 (UTC) Received: from ausb3twp01.amd.com (163.181.249.108) by TX2EHSMHS021.bigfish.com (10.9.99.121) with Microsoft SMTP Server id 14.1.225.8; Mon, 11 Apr 2011 09:32:10 +0000 X-WSS-ID: 0LJHEHJ-01-B1R-02 X-M-MSG: Received: from sausexedgep01.amd.com (sausexedgep01-ext.amd.com [163.181.249.72]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ausb3twp01.amd.com (Axway MailGate 3.8.1) with ESMTP id 2D86A10281A1; Mon, 11 Apr 2011 04:32:07 -0500 (CDT) Received: from sausexhtp01.amd.com (163.181.3.165) by sausexedgep01.amd.com (163.181.36.54) with Microsoft SMTP Server (TLS) id 8.3.106.1; Mon, 11 Apr 2011 04:32:44 -0500 Received: from storexhtp01.amd.com (172.24.4.3) by sausexhtp01.amd.com (163.181.3.165) with Microsoft SMTP Server (TLS) id 8.3.83.0; Mon, 11 Apr 2011 04:32:07 -0500 Received: from gwo.osrc.amd.com (165.204.16.204) by storexhtp01.amd.com (172.24.4.3) with Microsoft SMTP Server id 8.3.83.0; Mon, 11 Apr 2011 05:32:06 -0400 Received: from lemmy.osrc.amd.com (lemmy.osrc.amd.com [165.204.15.93]) by gwo.osrc.amd.com (Postfix) with ESMTP id ABF9C49C59B; Mon, 11 Apr 2011 10:32:05 +0100 (BST) Received: by lemmy.osrc.amd.com (Postfix, from userid 1000) id 9B077FFC68; Mon, 11 Apr 2011 11:32:05 +0200 (CEST) From: Joerg Roedel To: CC: , , Joerg Roedel Subject: [PATCH 2/2] x86/amd-iommu: Add support for invalidate_all command Date: Mon, 11 Apr 2011 11:32:04 +0200 Message-ID: <1302514324-14717-3-git-send-email-joerg.roedel@amd.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1302514324-14717-1-git-send-email-joerg.roedel@amd.com> References: <1302514324-14717-1-git-send-email-joerg.roedel@amd.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 11 Apr 2011 09:32:51 +0000 (UTC) This patch adds support for the invalidate_all command present in new versions of the AMD IOMMU. Signed-off-by: Joerg Roedel --- arch/x86/include/asm/amd_iommu_types.h | 1 + arch/x86/kernel/amd_iommu.c | 24 ++++++++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h index 5c24e46..df62d26 100644 --- a/arch/x86/include/asm/amd_iommu_types.h +++ b/arch/x86/include/asm/amd_iommu_types.h @@ -127,6 +127,7 @@ #define CMD_COMPL_WAIT 0x01 #define CMD_INV_DEV_ENTRY 0x02 #define CMD_INV_IOMMU_PAGES 0x03 +#define CMD_INV_ALL 0x08 #define CMD_COMPL_WAIT_STORE_MASK 0x01 #define CMD_COMPL_WAIT_INT_MASK 0x02 diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c index d609610..a9b5cf7 100644 --- a/arch/x86/kernel/amd_iommu.c +++ b/arch/x86/kernel/amd_iommu.c @@ -463,6 +463,12 @@ static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; } +static void build_inv_all(struct iommu_cmd *cmd) +{ + memset(cmd, 0, sizeof(*cmd)); + CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); +} + /* * Writes the command to the IOMMUs command buffer and informs the * hardware about the new command. @@ -567,10 +573,24 @@ static void iommu_flush_tlb_all(struct amd_iommu *iommu) iommu_completion_wait(iommu); } +static void iommu_flush_all(struct amd_iommu *iommu) +{ + struct iommu_cmd cmd; + + build_inv_all(&cmd); + + iommu_queue_command(iommu, &cmd); + iommu_completion_wait(iommu); +} + void iommu_flush_all_caches(struct amd_iommu *iommu) { - iommu_flush_dte_all(iommu); - iommu_flush_tlb_all(iommu); + if (iommu_feature(iommu, FEATURE_IA)) { + iommu_flush_all(iommu); + } else { + iommu_flush_dte_all(iommu); + iommu_flush_tlb_all(iommu); + } } /*