From patchwork Fri Sep 2 00:25:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 1120902 X-Patchwork-Delegate: bhelgaas@google.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p820PI3G012775 for ; Fri, 2 Sep 2011 00:25:19 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932740Ab1IBAZR (ORCPT ); Thu, 1 Sep 2011 20:25:17 -0400 Received: from mail-gw0-f46.google.com ([74.125.83.46]:55274 "EHLO mail-gw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932742Ab1IBAZQ (ORCPT ); Thu, 1 Sep 2011 20:25:16 -0400 Received: by gwaa12 with SMTP id a12so1332847gwa.19 for ; Thu, 01 Sep 2011 17:25:14 -0700 (PDT) Received: by 10.90.167.5 with SMTP id p5mr233357age.40.1314923114173; Thu, 01 Sep 2011 17:25:14 -0700 (PDT) Received: from scylla (cpe-70-113-48-102.austin.res.rr.com [70.113.48.102]) by mx.google.com with ESMTPS id o23sm1107480yhk.3.2011.09.01.17.25.12 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 01 Sep 2011 17:25:13 -0700 (PDT) Received: by scylla (sSMTP sendmail emulation); Thu, 1 Sep 2011 19:25:11 -0500 From: Jon Mason To: Jesse Barnes Cc: linux-pci@vger.kernel.org Subject: [PATCH] PCI: Remove MRRS modification from MPS setting code Date: Thu, 1 Sep 2011 19:25:11 -0500 Message-Id: <1314923111-20318-1-git-send-email-mason@myri.com> X-Mailer: git-send-email 1.7.6 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 02 Sep 2011 00:25:19 +0000 (UTC) Modifying the Maximum Read Request Size to 0 (value of 128Bytes) has massive negative ramifications on some devices. Without knowing which devices have this issue, do not modify from the default value when walking the PCI-E bus. Signed-off-by: Jon Mason --- drivers/pci/probe.c | 36 ------------------------------------ 1 files changed, 0 insertions(+), 36 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 8473727..d896c5e 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1394,41 +1394,6 @@ static void pcie_write_mps(struct pci_dev *dev, int mps) dev_err(&dev->dev, "Failed attempting to set the MPS\n"); } -static void pcie_write_mrrs(struct pci_dev *dev, int mps) -{ - int rc, mrrs; - - if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { - int dev_mpss = 128 << dev->pcie_mpss; - - /* For Max performance, the MRRS must be set to the largest - * supported value. However, it cannot be configured larger - * than the MPS the device or the bus can support. This assumes - * that the largest MRRS available on the device cannot be - * smaller than the device MPSS. - */ - mrrs = mps < dev_mpss ? mps : dev_mpss; - } else - /* In the "safe" case, configure the MRRS for fairness on the - * bus by making all devices have the same size - */ - mrrs = mps; - - - /* MRRS is a R/W register. Invalid values can be written, but a - * subsiquent read will verify if the value is acceptable or not. - * If the MRRS value provided is not acceptable (e.g., too large), - * shrink the value until it is acceptable to the HW. - */ - while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { - rc = pcie_set_readrq(dev, mrrs); - if (rc) - dev_err(&dev->dev, "Failed attempting to set the MRRS\n"); - - mrrs /= 2; - } -} - static int pcie_bus_configure_set(struct pci_dev *dev, void *data) { int mps = 128 << *(u8 *)data; @@ -1440,7 +1405,6 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data) pcie_get_mps(dev), 128<pcie_mpss, pcie_get_readrq(dev)); pcie_write_mps(dev, mps); - pcie_write_mrrs(dev, mps); dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", pcie_get_mps(dev), 128<pcie_mpss, pcie_get_readrq(dev));