From patchwork Tue Jul 10 15:54:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 1178141 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 4DA91402D2 for ; Tue, 10 Jul 2012 15:57:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756085Ab2GJP4e (ORCPT ); Tue, 10 Jul 2012 11:56:34 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:43454 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752464Ab2GJP4a (ORCPT ); Tue, 10 Jul 2012 11:56:30 -0400 Received: by mail-pb0-f46.google.com with SMTP id rp8so456687pbb.19 for ; Tue, 10 Jul 2012 08:56:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references; bh=gvx9ZWCq0bDfjis0L01hcLxmR4hLD9XjgQbkcQsNU88=; b=kU8dNOKPlhoHa24PdWaL1o63SMS9IyjKFvchbp+v8/yf2ZdrjIa4pOaEY3q+oTBboL MvsJXB3VB6Xmo2UzhtxQ0I7S5XpMFNIapeNuar82hwVdleQOJo4nohbKduyKYkfcOkPS vswL92OnnS5W3PJPq/8UO1fbA+8sJpOXr9fJRg2OZubTD2Cb10fdVQj9wrl6+2grqJGh TtTHhdGQsMrFrNEb1C0exODXuGNCaomdalyc3XSIotwbwOhjuFS4TS5CQi2cM5FcIEgt T2t9G3GUKQS0eZd/ofxQz892AG7dEFGBW7X7ANlyhuTMr4fKL2Z+4/rIDwyk5ubf43kG pLBw== Received: by 10.68.221.227 with SMTP id qh3mr69963450pbc.115.1341935790354; Tue, 10 Jul 2012 08:56:30 -0700 (PDT) Received: from localhost.localdomain ([221.221.21.23]) by mx.google.com with ESMTPS id oq4sm3056662pbb.21.2012.07.10.08.56.21 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 10 Jul 2012 08:56:29 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , Keping Chen , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [RFC PATCH 11/14] AER/PCI: use PCIe cap access functions to simplify implementation Date: Tue, 10 Jul 2012 23:54:12 +0800 Message-Id: <1341935655-5381-12-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341935655-5381-1-git-send-email-jiang.liu@huawei.com> References: <1341935655-5381-1-git-send-email-jiang.liu@huawei.com> In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe cap access functions to simplify PCI AER implementation. Signed-off-by: Jiang Liu Signed-off-by: Yijing Wang --- drivers/pci/pcie/aer/aerdrv.c | 16 ++++++------- drivers/pci/pcie/aer/aerdrv_core.c | 45 ++++++++++++++---------------------- 2 files changed, 24 insertions(+), 37 deletions(-) diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index f7c6245..27ec1bb 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -122,19 +122,18 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev, static void aer_enable_rootport(struct aer_rpc *rpc) { struct pci_dev *pdev = rpc->rpd->port; - int pos, aer_pos; + int aer_pos; u16 reg16; u32 reg32; - pos = pci_pcie_cap(pdev); /* Clear PCIe Capability's Device Status */ - pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16); - pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16); + pci_pcie_cap_read_word(pdev, PCI_EXP_DEVSTA, ®16); + pci_pcie_cap_write_word(pdev, PCI_EXP_DEVSTA, reg16); /* Disable system error generation in response to error messages */ - pci_read_config_word(pdev, pos + PCI_EXP_RTCTL, ®16); + pci_pcie_cap_read_word(pdev, PCI_EXP_RTCTL, ®16); reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK); - pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16); + pci_pcie_cap_write_word(pdev, PCI_EXP_RTCTL, reg16); aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); /* Clear error status */ @@ -396,9 +395,8 @@ static void aer_error_resume(struct pci_dev *dev) u16 reg16; /* Clean up Root device status */ - pos = pci_pcie_cap(dev); - pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16); - pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16); + pci_pcie_cap_read_word(dev, PCI_EXP_DEVSTA, ®16); + pci_pcie_cap_write_word(dev, PCI_EXP_DEVSTA, reg16); /* Clean AER Root Error Status */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index f551534..5671fce 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -35,25 +35,20 @@ module_param(nosourceid, bool, 0); int pci_enable_pcie_error_reporting(struct pci_dev *dev) { u16 reg16 = 0; - int pos; if (pcie_aer_get_firmware_first(dev)) return -EIO; - pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); - if (!pos) - return -EIO; - - pos = pci_pcie_cap(dev); - if (!pos) + if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) return -EIO; - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16); - reg16 |= (PCI_EXP_DEVCTL_CERE | - PCI_EXP_DEVCTL_NFERE | - PCI_EXP_DEVCTL_FERE | - PCI_EXP_DEVCTL_URRE); - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16); + if (!pci_pcie_cap_read_word(dev, PCI_EXP_DEVCTL, ®16)) { + reg16 |= (PCI_EXP_DEVCTL_CERE | + PCI_EXP_DEVCTL_NFERE | + PCI_EXP_DEVCTL_FERE | + PCI_EXP_DEVCTL_URRE); + pci_pcie_cap_write_word(dev, PCI_EXP_DEVCTL, reg16); + } return 0; } @@ -62,21 +57,17 @@ EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); int pci_disable_pcie_error_reporting(struct pci_dev *dev) { u16 reg16 = 0; - int pos; if (pcie_aer_get_firmware_first(dev)) return -EIO; - pos = pci_pcie_cap(dev); - if (!pos) - return -EIO; - - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16); - reg16 &= ~(PCI_EXP_DEVCTL_CERE | - PCI_EXP_DEVCTL_NFERE | - PCI_EXP_DEVCTL_FERE | - PCI_EXP_DEVCTL_URRE); - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16); + if (!pci_pcie_cap_read_word(dev, PCI_EXP_DEVCTL, ®16)) { + reg16 &= ~(PCI_EXP_DEVCTL_CERE | + PCI_EXP_DEVCTL_NFERE | + PCI_EXP_DEVCTL_FERE | + PCI_EXP_DEVCTL_URRE); + pci_pcie_cap_write_word(dev, PCI_EXP_DEVCTL, reg16); + } return 0; } @@ -151,18 +142,16 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) */ if (atomic_read(&dev->enable_cnt) == 0) return false; - pos = pci_pcie_cap(dev); - if (!pos) - return false; /* Check if AER is enabled */ - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16); + pci_pcie_cap_read_word(dev, PCI_EXP_DEVCTL, ®16); if (!(reg16 & ( PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE))) return false; + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (!pos) return false;