From patchwork Tue Jul 24 16:41:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 1232451 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 10D903FD4F for ; Tue, 24 Jul 2012 16:43:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755020Ab2GXQnT (ORCPT ); Tue, 24 Jul 2012 12:43:19 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:64865 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754957Ab2GXQnS (ORCPT ); Tue, 24 Jul 2012 12:43:18 -0400 Received: by pbbrp8 with SMTP id rp8so12926361pbb.19 for ; Tue, 24 Jul 2012 09:43:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=e4CqUo3owQzz3nsLrqgBuhH13+Hshok2U4Lvww7tzrc=; b=YR79JmkF9AqM8+0M7FNmNrLwV/cwKJjRo6yo8U6HfiVG70XHaDzvEaW+bqFB2oWFyE kQ5zlVr1kL7AML+Bzb513XoDzWAz/+4HvvOf+ldVcXGMpUHHMWzGGsXYI3Zcz2k4G5ly JTkVB/n5ra4dM/fS/Tz8JlgeNBtjpzxO6h0ypvuvkpH8nfzMK8fpHZ8YHzhEVJZ2nC3v wHgHUXbAMdrJalfvKQki/RgwHvKjvV5NetN+pTEeIAYroJDoQnEoe0Y4+hiVt+wbNfaZ flQViTEXSykYv6dMBLXCjYxXHwyo8Q6HkdO9Fxc+cgJ0sw5GYehFn/9e4qoVnyrxyKFT Ooww== Received: by 10.68.236.129 with SMTP id uu1mr45987843pbc.77.1343148197507; Tue, 24 Jul 2012 09:43:17 -0700 (PDT) Received: from localhost.localdomain ([221.221.26.244]) by mx.google.com with ESMTPS id wk10sm7863878pbc.71.2012.07.24.09.43.08 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jul 2012 09:43:16 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [RFC PATCH v2 24/32] PCI/ath9k: use PCIe capabilities access functions to simplify implementation Date: Wed, 25 Jul 2012 00:41:09 +0800 Message-Id: <1343148077-25941-1-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify ath9k driver's implementation. Signed-off-by: Jiang Liu --- drivers/net/wireless/ath/ath9k/pci.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index a856b51..f90342d 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c @@ -112,11 +112,9 @@ static void ath_pci_aspm_init(struct ath_common *common) struct ath_hw *ah = sc->sc_ah; struct pci_dev *pdev = to_pci_dev(sc->dev); struct pci_dev *parent; - int pos; - u8 aspm; + u16 aspm; - pos = pci_pcie_cap(pdev); - if (!pos) + if (!pci_is_pcie(pdev)) return; parent = pdev->bus->self; @@ -125,24 +123,22 @@ static void ath_pci_aspm_init(struct ath_common *common) if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { /* Bluetooth coexistance requires disabling ASPM. */ - pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm); + pci_pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &aspm); aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); - pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm); + pci_pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, aspm); /* * Both upstream and downstream PCIe components should * have the same ASPM settings. */ - pos = pci_pcie_cap(parent); - pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); + pci_pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); - pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm); + pci_pcie_capability_write_word(parent, PCI_EXP_LNKCTL, aspm); return; } - pos = pci_pcie_cap(parent); - pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); + pci_pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { ah->aspm_enabled = true; /* Initialize PCIe PM and SERDES registers. */