From patchwork Wed Aug 1 15:54:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 1265191 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 6003D3FC81 for ; Wed, 1 Aug 2012 16:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755579Ab2HAP6v (ORCPT ); Wed, 1 Aug 2012 11:58:51 -0400 Received: from mail-yx0-f174.google.com ([209.85.213.174]:61462 "EHLO mail-yx0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755556Ab2HAP6t (ORCPT ); Wed, 1 Aug 2012 11:58:49 -0400 Received: by mail-yx0-f174.google.com with SMTP id l2so7449160yen.19 for ; Wed, 01 Aug 2012 08:58:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=o8T4dJmkAVhSWEq2kPXjUAZztSkMKw0S/ltVum5rJMU=; b=J0o7CXNKmK0meiEX4Zb6RILaQ2At7sQt9RrF3npkSBDkdv9tUmw+/A1efJcmqkTNPo jvOuf4NK6w652TPN0/fhTebWkXkRocM6LhmtUzInbhndV7W6is6RbRe2aItw36ZXS5lc W0iyM68ncGDjpFIP5sqAhMDI7Tvck8nydA+Q3D7D5gXLtto7K/l8XD/UwIz8dous3W7P U160RY0mEdo04xTCwfs9LQLZcZ0jn62yPDUv6DGXhXiqb7bJVYRertqoAsK+tCwFb31i Ekl3KAwQ6ErCAqyPszLbrG6e2nKWjr5aJ6d7TEvMKjfRc1zcgwzopjgYnO9Xq/oouRE0 IUDw== Received: by 10.66.79.195 with SMTP id l3mr40933561pax.33.1343836728880; Wed, 01 Aug 2012 08:58:48 -0700 (PDT) Received: from localhost.localdomain ([58.250.81.2]) by mx.google.com with ESMTPS id pe8sm2816231pbc.76.2012.08.01.08.58.39 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 01 Aug 2012 08:58:47 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile , Divy Le Ray , Dimitris Michailidis Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [PATCH v3 22/32] PCI/chelsio: use PCIe capabilities access functions to simplify implementation Date: Wed, 1 Aug 2012 23:54:27 +0800 Message-Id: <1343836477-7287-23-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify chelsio ethernet drivers' implementation. Signed-off-by: Jiang Liu --- drivers/net/ethernet/chelsio/cxgb3/t3_hw.c | 19 +++++++------------ drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 11 ++--------- drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 10 +++------- 3 files changed, 12 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c index 44ac2f4..8fadbb3 100644 --- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c @@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap) unsigned int log2_width, pldsize; unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; - pci_read_config_word(adap->pdev, - adap->pdev->pcie_cap + PCI_EXP_DEVCTL, - &val); + pci_pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val); pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; pci_read_config_word(adap->pdev, 0x2, &devid); if (devid == 0x37) { - pci_write_config_word(adap->pdev, - adap->pdev->pcie_cap + PCI_EXP_DEVCTL, + pci_pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL, val & ~PCI_EXP_DEVCTL_READRQ & ~PCI_EXP_DEVCTL_PAYLOAD); pldsize = 0; } - pci_read_config_word(adap->pdev, adap->pdev->pcie_cap + PCI_EXP_LNKCTL, - &val); + pci_pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val); fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0)); fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : @@ -3425,15 +3421,14 @@ out_err: static void get_pci_mode(struct adapter *adapter, struct pci_params *p) { static unsigned short speed_map[] = { 33, 66, 100, 133 }; - u32 pci_mode, pcie_cap; + u32 pci_mode; - pcie_cap = pci_pcie_cap(adapter->pdev); - if (pcie_cap) { + if (pci_is_pcie(adapter->pdev)) { u16 val; p->variant = PCI_VARIANT_PCIE; - pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, - &val); + pci_pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, + &val); p->width = (val >> 4) & 0x3f; return; } diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c index e1f96fb..a414bac 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c @@ -3694,15 +3694,8 @@ static void __devinit print_port_info(const struct net_device *dev) static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev) { - u16 v; - int pos; - - pos = pci_pcie_cap(dev); - if (pos > 0) { - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &v); - v |= PCI_EXP_DEVCTL_RELAX_EN; - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, v); - } + pci_pcie_capability_change_word(dev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_RELAX_EN, 0); } /* diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c index 32e1dd5..f0e673e 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c @@ -2741,14 +2741,10 @@ static void __devinit get_pci_mode(struct adapter *adapter, struct pci_params *p) { u16 val; - u32 pcie_cap = pci_pcie_cap(adapter->pdev); - if (pcie_cap) { - pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, - &val); - p->speed = val & PCI_EXP_LNKSTA_CLS; - p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; - } + pci_pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); + p->speed = val & PCI_EXP_LNKSTA_CLS; + p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; } /**