From patchwork Wed Aug 1 15:54:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 1265311 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 480BBDF215 for ; Wed, 1 Aug 2012 16:04:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754700Ab2HAP4X (ORCPT ); Wed, 1 Aug 2012 11:56:23 -0400 Received: from mail-gh0-f174.google.com ([209.85.160.174]:57673 "EHLO mail-gh0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753913Ab2HAP4U (ORCPT ); Wed, 1 Aug 2012 11:56:20 -0400 Received: by ghrr11 with SMTP id r11so984595ghr.19 for ; Wed, 01 Aug 2012 08:56:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=fNGe8l1bRT3r6nVv3U9LZydgolkFfVeu0Cvxgsvnq/I=; b=D7Wxjv1oTpv18a01o9xqjSHefqvRUrohJgsBQJDM8qTZQ0hshMxbTqJEVHkcqgf8dx SJ+6GPGVyPXh35PZGlEoFfnSsMwUUVNsEZkZnGdm46IgvgJgsABUAWETTd/2B/owq5wy zAJQzTVRQCZN0NUMwbqyQX8iOp9YoG04hZWqYOaMbWGBjx3mrdYbgyd0TPSx/Q4//uFx EyIWL2oCxktt7R2sUJlcBZu+YG228OIxnkwUtVaGuj0c+5cnPV1Yi8E/OnaiUobMNudN Rw8IKhZuAYF4GZ7I1+O1sMwsmjBzYQfWe2gxLvGEUA8hiUY7MT772pHoSViPuomm2TrO qIdg== Received: by 10.66.85.135 with SMTP id h7mr40705676paz.75.1343836579968; Wed, 01 Aug 2012 08:56:19 -0700 (PDT) Received: from localhost.localdomain ([58.250.81.2]) by mx.google.com with ESMTPS id pe8sm2816231pbc.76.2012.08.01.08.56.13 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 01 Aug 2012 08:56:19 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [PATCH v3 07/32] PCI/portdrv: use PCIe capabilities access functions to simplify implementation Date: Wed, 1 Aug 2012 23:54:12 +0800 Message-Id: <1343836477-7287-8-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify PCIe portdrv implementation. Signed-off-by: Jiang Liu Signed-off-by: Yijing Wang Reviewed-by: Kenji Kaneshige --- drivers/pci/pcie/portdrv_core.c | 15 +++++---------- drivers/pci/pcie/portdrv_pci.c | 10 ++-------- 2 files changed, 7 insertions(+), 18 deletions(-) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index bf320a9..274d524 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -246,8 +246,7 @@ static void cleanup_service_irqs(struct pci_dev *dev) */ static int get_port_device_capability(struct pci_dev *dev) { - int services = 0, pos; - u16 reg16; + int services = 0; u32 reg32; int cap_mask = 0; int err; @@ -265,11 +264,9 @@ static int get_port_device_capability(struct pci_dev *dev) return 0; } - pos = pci_pcie_cap(dev); - pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); /* Hot-Plug Capable */ - if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) { - pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, ®32); + if ((cap_mask & PCIE_PORT_SERVICE_HP)) { + pci_pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, ®32); if (reg32 & PCI_EXP_SLTCAP_HPC) { services |= PCIE_PORT_SERVICE_HP; /* @@ -277,10 +274,8 @@ static int get_port_device_capability(struct pci_dev *dev) * enabled by the BIOS and the hot-plug service driver * is not loaded. */ - pos += PCI_EXP_SLTCTL; - pci_read_config_word(dev, pos, ®16); - reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE); - pci_write_config_word(dev, pos, reg16); + pci_pcie_capability_change_word(dev, PCI_EXP_SLTCTL, + 0, PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE); } } /* AER capable */ diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c index 24d1463..93f726c 100644 --- a/drivers/pci/pcie/portdrv_pci.c +++ b/drivers/pci/pcie/portdrv_pci.c @@ -64,14 +64,8 @@ __setup("pcie_ports=", pcie_port_setup); */ void pcie_clear_root_pme_status(struct pci_dev *dev) { - int rtsta_pos; - u32 rtsta; - - rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA; - - pci_read_config_dword(dev, rtsta_pos, &rtsta); - rtsta |= PCI_EXP_RTSTA_PME; - pci_write_config_dword(dev, rtsta_pos, rtsta); + pci_pcie_capability_change_dword(dev, PCI_EXP_RTSTA, + PCI_EXP_RTSTA_PME, 0); } static int pcie_portdrv_restore_config(struct pci_dev *dev)