From patchwork Fri Jan 18 16:07:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 2003741 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 4CB6BDFB78 for ; Fri, 18 Jan 2013 16:09:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755483Ab3ARQIc (ORCPT ); Fri, 18 Jan 2013 11:08:32 -0500 Received: from mail-pa0-f51.google.com ([209.85.220.51]:65527 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755345Ab3ARQIb (ORCPT ); Fri, 18 Jan 2013 11:08:31 -0500 Received: by mail-pa0-f51.google.com with SMTP id fb11so2209171pad.10 for ; Fri, 18 Jan 2013 08:08:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=rwTF3q2zuL703nu2N1ifLaJ5oVGc4jZl96o6sla1+QA=; b=BpgPAqnPbPex/FLfyyoYxRllzfhdhE8+EvXjIz6kqs0ZGs1WcRvxyole8OP/XwnvNN xzeLh38G9Pgf/j+OluNj0ZIlywuIyi8+ixe2TAVPYr1wXf/s0B5F7n+P3DpOKXRILiN4 zMNWBM+R5x/QjY4/N60fDpfpsOcQs1O4BpVig2SSf9bx64iF3frWfi6Y5jCbmAhQWaYX Fm7FtmnSJTLQ0Lv6V3hCBTFuU/9u/K9jgus5HW65g4PxZMTn29r6ulyxgaRzAap3HHuJ G7maON8h6OuWeywUG/lEH3vsXnftd51JFXSLvAIYc7uPb1+w4F6/Oa7ElT7axBPKPHQK dU3g== X-Received: by 10.66.74.197 with SMTP id w5mr24950871pav.60.1358525310141; Fri, 18 Jan 2013 08:08:30 -0800 (PST) Received: from localhost.localdomain ([120.197.109.98]) by mx.google.com with ESMTPS id ux4sm3320742pbc.25.2013.01.18.08.08.26 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 18 Jan 2013 08:08:29 -0800 (PST) From: Jiang Liu To: "Rafael J . Wysocki" , Bjorn Helgaas Cc: Jiang Liu , Yinghai Lu , Kenji Kaneshige , Yijing Wang , Jiang Liu , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Greg Kroah-Hartman , ACPI Devel Maling List , Toshi Kani , Myron Stowe Subject: [RFC PATCH v5 7/8] PCI/PCIe: add "pci=nopciehp" to disable PCIe native hotplug Date: Sat, 19 Jan 2013 00:07:45 +0800 Message-Id: <1358525267-14268-8-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358525267-14268-1-git-send-email-jiang.liu@huawei.com> References: <1358525267-14268-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If user specifies "pci=nopciehp" on kernel boot command line, OSPM won't claim PCIe native hotplug service from firmware and no PCIe port devices will be created for PCIe native hotplug service. Signed-off-by: Jiang Liu --- Documentation/kernel-parameters.txt | 2 ++ drivers/acpi/pci_root.c | 3 ++- drivers/pci/pci.c | 2 ++ drivers/pci/pcie/portdrv_core.c | 5 +++-- drivers/pci/pcie/portdrv_pci.c | 3 +++ include/linux/pci.h | 9 +++++++++ 6 files changed, 21 insertions(+), 3 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 9776f06..28dd0ad 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2106,6 +2106,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. noaer [PCIE] If the PCIEAER kernel config parameter is enabled, this kernel boot option can be used to disable the use of PCIE advanced error reporting. + nopciehp [PCIE] this kernel boot option can be used to + disable PCIe native hotplug. nodomains [PCI] Disable support for multiple PCI root domains (aka PCI segments, in ACPI-speak). nommconf [X86] Disable use of MMCONFIG for PCI diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index c6200ff..c37eedb 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -551,8 +551,9 @@ static int __devinit acpi_pci_root_add(struct acpi_device *device) if (!pcie_ports_disabled && (flags & ACPI_PCIE_REQ_SUPPORT) == ACPI_PCIE_REQ_SUPPORT) { flags = OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL - | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | OSC_PCI_EXPRESS_PME_CONTROL; + if (!pcie_native_hotplug_disabled) + flags |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL; if (pci_aer_available()) { if (aer_acpi_firmware_first()) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 2f8f4c6..34b2c83 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3869,6 +3869,8 @@ static int __init pci_setup(char *str) pci_no_msi(); } else if (!strcmp(str, "noaer")) { pci_no_aer(); + } else if (!strcmp(str, "nopciehp")) { + pcie_no_native_hotplug(); } else if (!strncmp(str, "realloc=", 8)) { pci_realloc_get_opt(str + 8); } else if (!strncmp(str, "realloc", 7)) { diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index ed129b4..e7e1679 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -263,8 +263,9 @@ static int get_port_device_capability(struct pci_dev *dev) err = pcie_port_platform_notify(dev, &cap_mask); if (!pcie_ports_auto) { - cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP - | PCIE_PORT_SERVICE_VC; + cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_VC; + if (!pcie_native_hotplug_disabled) + cap_mask |= PCIE_PORT_SERVICE_HP; if (pci_aer_available()) cap_mask |= PCIE_PORT_SERVICE_AER; } else if (err) { diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c index 0761d90..018cee0 100644 --- a/drivers/pci/pcie/portdrv_pci.c +++ b/drivers/pci/pcie/portdrv_pci.c @@ -40,6 +40,9 @@ bool pcie_ports_disabled; */ bool pcie_ports_auto = true; +/* If set, the PCIe native hotplug will not be used. */ +bool pcie_native_hotplug_disabled; + static int __init pcie_port_setup(char *str) { if (!strncmp(str, "compat", 6)) { diff --git a/include/linux/pci.h b/include/linux/pci.h index 12e5447..715e17b 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1138,9 +1138,18 @@ extern int pci_msi_enabled(void); #ifdef CONFIG_PCIEPORTBUS extern bool pcie_ports_disabled; extern bool pcie_ports_auto; +extern bool pcie_native_hotplug_disabled; + +static inline void pcie_no_native_hotplug(void) +{ + pcie_native_hotplug_disabled = true; +} #else #define pcie_ports_disabled true #define pcie_ports_auto false +#define pcie_native_hotplug_disabled true + +static inline void pcie_no_native_hotplug(void) { } #endif #ifndef CONFIG_PCIEASPM